Zeeshan Ali Email & Phone Number | Zeeshan has keen interest in computer architecture and microarchitecture. He constantly aims to gain expertise in the various domains of hardware design verification. He worked with SiFive design verification team where he developed and implemented verification plan for Sv48 virtual memory system for SiFive linux capable RISCV processors. He worked on coverage closure of SiFive Core IP 21G1 & 21G2 releases. He also worked with Akeana where his primary responsibilities were architectural and micro-architectural verification/coverage of IFU and Decode units of state of the art high performance RISC-V based superscalar out of order processors. He also worked with Barcelona Supercomputing Center as a RISCV CPU verification engineer. Zeeshan holds Bachelor's degree in Electrical/Electronics Engineering from Nust School of Electrical Engineering and Computer Science (SEECS) Islamabad, Pakistan.

Zeeshan Ali

Zeeshan has keen interest in computer architecture and microarchitecture. He constantly aims to gain...
Cork Metropolitan Area, Cork Metropolitan Area, Ireland

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Zeeshan Ali’s Email zali@zenosemi.com

Zeeshan Ali’s Phone Numbers +1 650-575-****

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Zeeshan Ali’s Location Cork Metropolitan Area, Cork Metropolitan Area, Ireland

Zeeshan Ali’s Current Industry Qualcomm

Zeeshan Ali’s Prior Industry Barcelona Supercomputing Center | Aql Tech Solutions | Lampro Mellon

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Work Experience

Qualcomm

Design Verification Engineer

2023-10-01 00:00:00 - Present

Barcelona Supercomputing Center

Design Verification Engineer

2023-04-01 00:00:00 - 2023-10-01 00:00:00

Aql Tech Solutions

Design Verification Engineer

2021-11-01 00:00:00 - 2023-03-01 00:00:00

Lampro Mellon

Associate Design Verification Engineer

2020-10-01 00:00:00 - 2021-11-01 00:00:00

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Languages

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FAQ About Zeeshan Ali

Zeeshan Ali is located at
Cork Metropolitan Area, Cork Metropolitan Area, Ireland

Zeeshan Ali is a Zeeshan has keen interest in computer architecture and microarchitecture. He constantly aims to gain expertise in the various domains of hardware design verification. He worked with SiFive design verification team where he developed and implemented verification plan for Sv48 virtual memory system for SiFive linux capable RISCV processors. He worked on coverage closure of SiFive Core IP 21G1 & 21G2 releases. He also worked with Akeana where his primary responsibilities were architectural and micro-architectural verification/coverage of IFU and Decode units of state of the art high performance RISC-V based superscalar out of order processors. He also worked with Barcelona Supercomputing Center as a RISCV CPU verification engineer. Zeeshan holds Bachelor's degree in Electrical/Electronics Engineering from Nust School of Electrical Engineering and Computer Science (SEECS) Islamabad, Pakistan.