YuanHao Tung Email & Phone Number | Engineering Professional with over 7.5 years experience in Physical layer algorithm design, system performance analysis, and verification; Mainly focus on digital-TV and ethernet related PHY layer system design; Co-working with hardware/algorithm teams in the United States, China, and Taiwan; Participate in 3GPP RAN6 EC-GSM-IoT Standardrization; Professional Strengths include: ● Analog Front-end Architecture Evaluation: Link-budget analysis ● Digital Front-end filter design: Rate Conversion and interference reduction filter design ● Inner receiver design: MMSE system performance evaluation; Equalization design: conventional DFE and its alternative design; Timing Recovery: Baud-rate and oversampling rate timing recovery design ● Outer receiver design: Convolutional/LDPC code encodee/decoder and turbo RS/Viterbi design Technical Skills ● Strong programming experience in C/C++ (12+ years) ● Automation of simulation test cases built-up and information parsing with Perl. ● Mathematical model simulation and analysis with MATLAB (12+ years)

YuanHao Tung

Engineering Professional with over 7.5 years experience in Physical layer algorithm design, system p...
Hsinchu City, Hsinchu City, Taiwan

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YuanHao Tung’s Location Hsinchu City, Hsinchu City, Taiwan

YuanHao Tung’s Current Industry Nvidia

YuanHao Tung’s Prior Industry Mediatek

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Mixed Signal System Architecture Engineer

2019-10-01 00:00:00 - Present

Technical Manager

2018-06-01 00:00:00 - 2019-10-01 00:00:00

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YuanHao Tung is a Engineering Professional with over 7.5 years experience in Physical layer algorithm design, system performance analysis, and verification; Mainly focus on digital-TV and ethernet related PHY layer system design; Co-working with hardware/algorithm teams in the United States, China, and Taiwan; Participate in 3GPP RAN6 EC-GSM-IoT Standardrization; Professional Strengths include: ● Analog Front-end Architecture Evaluation: Link-budget analysis ● Digital Front-end filter design: Rate Conversion and interference reduction filter design ● Inner receiver design: MMSE system performance evaluation; Equalization design: conventional DFE and its alternative design; Timing Recovery: Baud-rate and oversampling rate timing recovery design ● Outer receiver design: Convolutional/LDPC code encodee/decoder and turbo RS/Viterbi design Technical Skills ● Strong programming experience in C/C++ (12+ years) ● Automation of simulation test cases built-up and information parsing with Perl. ● Mathematical model simulation and analysis with MATLAB (12+ years)