Yinshen Wang Email & Phone Number | I am a second year MSEE student at Columbia University, majoring in digital circuits and hardware design. I will graduate on December 2014. Now I'm actively looking for full-time entry-level jobs of Digital Circuit Design and Verification, specifically in VLSI design, RTL design, ASIC design and FPGA development,System-Level design and verification.. Skill Set: -- In-depth knowledge of system-level design and verification, software simulation and virtual platforms, FPGA prototyping, models of computation, the SystemC language, transaction-level modeling, hardware-software partitioning, high-level synthesis, device drivers, on-chip communication architectures,integration of programmable cores and specialized accelerators. -- Good knowledge of ASIC Design and RTL design using Verilog HDL and System Verilog. -- Solid background knowledge of VLSI design and hands-on experience of Cadence Virtuoso schematic & layout development. -- Familiar with design tools: Synopsys Design Compiler, Modelsim, Synopsys Primetime; Cadence Encounter/Velocity, Cadence CTOS, Cadence Virtuoso; Mentor Questa. -- C/C++ coding, SystemC, System Verilog, Verilog, VHDL, SVA, OVL coding. -- Scripting language(Perl, TCL). Efficient and enthusiastic task execution, flexible problem solving skills. Contact Info: Email: yw2561@columbia.edu Tel :+8613520233715

Yinshen Wang

I am a second year MSEE student at Columbia University, majoring in digital circuits and hardware de...
Milpitas, California, United States

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Yinshen Wang’s Location Milpitas, California, United States

Yinshen Wang’s Current Industry Columbia University In The City Of New York

Yinshen Wang’s Prior Industry Harbin Institute Of Technology

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M.S.

2013-09-01 00:00:00 - Present

Graduate Research Assistant

2011-09-01 00:00:00 - 2013-07-01 00:00:00

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Yinshen Wang is a I am a second year MSEE student at Columbia University, majoring in digital circuits and hardware design. I will graduate on December 2014. Now I'm actively looking for full-time entry-level jobs of Digital Circuit Design and Verification, specifically in VLSI design, RTL design, ASIC design and FPGA development,System-Level design and verification.. Skill Set: -- In-depth knowledge of system-level design and verification, software simulation and virtual platforms, FPGA prototyping, models of computation, the SystemC language, transaction-level modeling, hardware-software partitioning, high-level synthesis, device drivers, on-chip communication architectures,integration of programmable cores and specialized accelerators. -- Good knowledge of ASIC Design and RTL design using Verilog HDL and System Verilog. -- Solid background knowledge of VLSI design and hands-on experience of Cadence Virtuoso schematic & layout development. -- Familiar with design tools: Synopsys Design Compiler, Modelsim, Synopsys Primetime; Cadence Encounter/Velocity, Cadence CTOS, Cadence Virtuoso; Mentor Questa. -- C/C++ coding, SystemC, System Verilog, Verilog, VHDL, SVA, OVL coding. -- Scripting language(Perl, TCL). Efficient and enthusiastic task execution, flexible problem solving skills. Contact Info: Email: yw2561@columbia.edu Tel :+8613520233715