Wei Zhang Email & Phone Number | In-depth Static Timing Analysis knowledge High speed sub-micron CMOS circuit implementation. Specialty include: Embedded Memory (SRAM, Register Array, CAM, etc.); Arithmetic unit and data path circuit; Clock generation circuit (PLL) and Distribution system; High speed I/O; Overall chip timing strategy and block architecture; Design and Simulation tool: various circuit simulators (HSPICE, HSIM, XA, BDASIM, Finesim) STA Tool: NanoTime, PrimeTime Computer Language: TCL.

Wei Zhang

In-depth Static Timing Analysis knowledge High speed sub-micron CMOS circuit implementation. Speci...
San Jose, California, United States

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Wei Zhang’s Location San Jose, California, United States

Wei Zhang’s Current Industry Apple

Wei Zhang’s Prior Industry Synopsys | Altera | Cypress Semiconductor | Lara Network | Hal Computer Systems

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ASIC Circuit Timing Advocate

2019-01-01 00:00:00 - Present

Application Consultant

2014-01-01 00:00:00 - 2019-01-01 00:00:00

Senior MTS

2004-01-01 00:00:00 - 2013-01-01 00:00:00

Principal Engineer / Staff Design Engineer

2001-01-01 00:00:00 - 2003-01-01 00:00:00

Senior Design Engineer

1998-01-01 00:00:00 - 2001-01-01 00:00:00

Senior Design Engineer

1992-01-01 00:00:00 - 1998-01-01 00:00:00

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Wei Zhang is a In-depth Static Timing Analysis knowledge High speed sub-micron CMOS circuit implementation. Specialty include: Embedded Memory (SRAM, Register Array, CAM, etc.); Arithmetic unit and data path circuit; Clock generation circuit (PLL) and Distribution system; High speed I/O; Overall chip timing strategy and block architecture; Design and Simulation tool: various circuit simulators (HSPICE, HSIM, XA, BDASIM, Finesim) STA Tool: NanoTime, PrimeTime Computer Language: TCL.