Vinayak Hegde Email & Phone Number | Email: vinayakshegde16@gmail.com Phone: 323-416-6625 9 years of experience in CPU/GPU/ASIC and Wireless SoC Physical Design. Specialization: - ASIC, CPU, GPU, Wireless SoC Physical Design - RTL to GDS - Physical-aware Synthesis - Place and Route - Static Timing Analysis (STA) and timing closure - Physical Verification (DRC/LVS) - Reliability Verification (IR/EM/Antenna) - Signal Integrity - Low power design - Flow methodology enhancement - Digital VLSI Design - Full custom and semi-custom designs Skills: - Languages & HDLs : Tcl, Perl, Shell, Verilog - EDA tools: Synopsys Fusion Compiler, ICC, ICC II, Primetime, Design Compiler, Cadence Virtuoso, Innovus, Encounter, Mentor Calibre, Apache Redhawk

Vinayak Hegde

Email: vinayakshegde16@gmail.com Phone: 323-416-6625 9 years of experience in CPU/GPU/ASIC and Wire...
San Francisco, California, United States

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Vinayak Hegde’s Email vhegde@amd.com

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Vinayak Hegde’s Location San Francisco, California, United States

Vinayak Hegde’s Current Industry Intel

Vinayak Hegde’s Prior Industry Amd | Oracle

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Physical Design Engineer

2022-08-01 00:00:00 - Present

MTS Silicon Design Engineer

2020-07-01 00:00:00 - 2022-08-01 00:00:00

Hardware Engineer

2015-01-01 00:00:00 - 2017-04-01 00:00:00

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Vinayak Hegde is a Email: vinayakshegde16@gmail.com Phone: 323-416-6625 9 years of experience in CPU/GPU/ASIC and Wireless SoC Physical Design. Specialization: - ASIC, CPU, GPU, Wireless SoC Physical Design - RTL to GDS - Physical-aware Synthesis - Place and Route - Static Timing Analysis (STA) and timing closure - Physical Verification (DRC/LVS) - Reliability Verification (IR/EM/Antenna) - Signal Integrity - Low power design - Flow methodology enhancement - Digital VLSI Design - Full custom and semi-custom designs Skills: - Languages & HDLs : Tcl, Perl, Shell, Verilog - EDA tools: Synopsys Fusion Compiler, ICC, ICC II, Primetime, Design Compiler, Cadence Virtuoso, Innovus, Encounter, Mentor Calibre, Apache Redhawk