Vijeth Anchatgeri Email & Phone Number | Highly motivated, self driven individual with a strong desire to pursue career in semiconductor industry, currently pursuing Masters in VLSI Design from R.V College of Engineering,Bangalore. My Skill sets include Strong Digital design. Good coding skills in Verilog HDL Knowledge of Static Timing Analysis(STA), ASIC Design Flow. Fair knowledge on Xilinx design tools (IP Core, Chipscope, ISE). Architecture’s ARM Cortex M3 and 8051. Knowledge on HDL Cosimulation and Simulink Models. EDA Tools Cadence Virtuoso ADE, Synopsys Design Compiler Synopsys Formality Synopsys VCS Cadence NC, Cadence Spectre, Mentor Graphics QuestaSim 6.4c and ModelSim6.3f Xilinx 10.1, ISE, Hardware Description Languages [HDL's] HDL Verilog - [IEEE Std 1364-2005] VHDL - [IEEE Std 1076-2008] System Verilog for Design - [IEEE Std 1800-2012] Scripting for Automation TCL

Vijeth Anchatgeri

Highly motivated, self driven individual with a strong desire to pursue career in semiconductor indu...
Bengaluru, Karnataka, India

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Vijeth Anchatgeri’s Location Bengaluru, Karnataka, India

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Design Engineer

Present

Senior Engineer, Soc Integration

2018-06-01 00:00:00 - 2018-09-01 00:00:00

Intern, R&D,Design Group

2015-01-01 00:00:00 - 2016-01-01 00:00:00

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Vijeth Anchatgeri is a Highly motivated, self driven individual with a strong desire to pursue career in semiconductor industry, currently pursuing Masters in VLSI Design from R.V College of Engineering,Bangalore. My Skill sets include Strong Digital design. Good coding skills in Verilog HDL Knowledge of Static Timing Analysis(STA), ASIC Design Flow. Fair knowledge on Xilinx design tools (IP Core, Chipscope, ISE). Architecture’s ARM Cortex M3 and 8051. Knowledge on HDL Cosimulation and Simulink Models. EDA Tools Cadence Virtuoso ADE, Synopsys Design Compiler Synopsys Formality Synopsys VCS Cadence NC, Cadence Spectre, Mentor Graphics QuestaSim 6.4c and ModelSim6.3f Xilinx 10.1, ISE, Hardware Description Languages [HDL's] HDL Verilog - [IEEE Std 1364-2005] VHDL - [IEEE Std 1076-2008] System Verilog for Design - [IEEE Std 1800-2012] Scripting for Automation TCL