Vignesh Swaminathan Email & Phone Number | I am currently working at Intel as a Design Verification and Emulation Engineer. I work in the Fullchip Verification team. o I am responsible for pre-silicon verification working closely with the Full chip Design Verification team and Emulation team using both the simulation and Emulation environment. o Worked with the team on a methodology to run UVM tests developed for simulation directly on Emulation model. o Verification lead for configuration features at fullchip o I am responsible for fullchip testbench development and releasing it to DV/Manufacturing teams I completed my Master's degree in the Electrical and Computer Engineering department of Portland State University specializing in Design Verification and Validation track. --------------------------------------------------------------------------------------------------------------------------------- TECHNICAL SKILLS • RTL Design and Verification : Verilog HDL, System Verilog, System Verilog Assertions, UVM. • Programming languages : C, C++. • EDA Tools : Synopsys VCS, Design Compiler, Mentor Visualizer, JasperGold. • Hardware : Veloce Emulator, 8085, 8086. • Scripting languages : Python, Perl, TCL. ------------------------------------------------------------------------------------------------------------------------------ Areas of interest: - Pre silicon Verification - Emulation - Using Machine learning for Verification

Vignesh Swaminathan

I am currently working at Intel as a Design Verification and Emulation Engineer. I work in the Fu...
San Jose, California, United States

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Vignesh Swaminathan’s Email vignesh.s@intel.com

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Vignesh Swaminathan’s Location San Jose, California, United States

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Vignesh Swaminathan’s Prior Industry Intel | Portland State University | Solartis | Oil And Natural Gas

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Vignesh Swaminathan is a I am currently working at Intel as a Design Verification and Emulation Engineer. I work in the Fullchip Verification team. o I am responsible for pre-silicon verification working closely with the Full chip Design Verification team and Emulation team using both the simulation and Emulation environment. o Worked with the team on a methodology to run UVM tests developed for simulation directly on Emulation model. o Verification lead for configuration features at fullchip o I am responsible for fullchip testbench development and releasing it to DV/Manufacturing teams I completed my Master's degree in the Electrical and Computer Engineering department of Portland State University specializing in Design Verification and Validation track. --------------------------------------------------------------------------------------------------------------------------------- TECHNICAL SKILLS • RTL Design and Verification : Verilog HDL, System Verilog, System Verilog Assertions, UVM. • Programming languages : C, C++. • EDA Tools : Synopsys VCS, Design Compiler, Mentor Visualizer, JasperGold. • Hardware : Veloce Emulator, 8085, 8086. • Scripting languages : Python, Perl, TCL. ------------------------------------------------------------------------------------------------------------------------------ Areas of interest: - Pre silicon Verification - Emulation - Using Machine learning for Verification - Computer Architecture