Vanita Iyer Email & Phone Number | In depth knowledge of PHY architectures used in high speed serial I/O’s like PCIE, SATA, USB, MIPI Experience in designing receiver clock path circuits like phase interpolator, CML2CMOS converters and quadrature clock generation schemes. In depth experience in high speed serial I/O DFT architecture and successful implementation on several Intel products. Post Silicon lab debug and validation experience on I/O’s used in many Intel products. Expert in DFT techniques like boundary scan (JTAG), BISTs, PRBS Excellent problem solving, debugging and analytical skills.

Vanita Iyer

In depth knowledge of PHY architectures used in high speed serial I/O’s like PCIE, SATA, USB, MIPI...
5204 Yorkton Way, San Jose, United States

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Vanita Iyer’s Email viyer@apple.com

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Vanita Iyer’s Location 5204 Yorkton Way, San Jose, United States

Vanita Iyer’s Current Industry Apple

Vanita Iyer’s Prior Industry Intel

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Engineering Program Manager

2021-08-01T00:00:00.000Z - Present

Senior Analog Design Engineer

2019-10-01T00:00:00.000Z - 2021-05-01T00:00:00.000Z

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Vanita Iyer is a In depth knowledge of PHY architectures used in high speed serial I/O’s like PCIE, SATA, USB, MIPI Experience in designing receiver clock path circuits like phase interpolator, CML2CMOS converters and quadrature clock generation schemes. In depth experience in high speed serial I/O DFT architecture and successful implementation on several Intel products. Post Silicon lab debug and validation experience on I/O’s used in many Intel products. Expert in DFT techniques like boundary scan (JTAG), BISTs, PRBS Excellent problem solving, debugging and analytical skills.