Tapas Nandy Email & Phone Number | - Design and management of High Speed Link PHY designs (HDMI, Mipi DPHY, MPHY, USB2/3, PCIe, Display Port, PAM4 based SERDES etc.) from architecture to silicon maturity of the IPs. This includes managing a team and coordinating cross-functional activities and stake holders spread across multiple countries. - Designed and managed analog and mixed signal IPs (e.g., ADC, DAC, Power management units, Oscillators, Thermal Sensors, various utility IPs and IOs for the SoCs). - Designed Semicustom ASICs (1990-1992). - Formed and grew and trained mixed-signal IP teams in India. Worked with multiple sites spanning across the multiple continents. Managed teams up to 75. - 33+ years of experience in semiconductor design and management field. - Holds Patents (12 granted, 2 filed) and International Conference Publications (9). - Delivered invited talks to renowned academic institutes and IEEE-SSCS Forum. - Senior Member (80259417), IEEE and Solid State Circuits Society. - Adjunct Faculty at IIT, Jodhpur from 2023. Specialties: High Speed Serial Link (Physical Layer) design and Analog and Mixed Signal circuits, Mixed-Signal IP development team development and management.

Tapas Nandy

- Design and management of High Speed Link PHY designs (HDMI, Mipi DPHY, MPHY, USB2/3, PCIe, Displa...
Bengaluru, Karnataka, India

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Tapas Nandy’s Location Bengaluru, Karnataka, India

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Engineering Director

2018-09-01 00:00:00 - Present

Director - R&D, High Speed PHY, Solutions Group

2015-03-01 00:00:00 - 2018-08-01 00:00:00

Sr. Group Manager - Analog & Mixed Signal IP/ High Speed Links PHYs

2009-01-01 00:00:00 - 2015-03-01 00:00:00

Member Techical Staff

1990-03-01 00:00:00 - 1992-10-01 00:00:00

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Tapas Nandy is a - Design and management of High Speed Link PHY designs (HDMI, Mipi DPHY, MPHY, USB2/3, PCIe, Display Port, PAM4 based SERDES etc.) from architecture to silicon maturity of the IPs. This includes managing a team and coordinating cross-functional activities and stake holders spread across multiple countries. - Designed and managed analog and mixed signal IPs (e.g., ADC, DAC, Power management units, Oscillators, Thermal Sensors, various utility IPs and IOs for the SoCs). - Designed Semicustom ASICs (1990-1992). - Formed and grew and trained mixed-signal IP teams in India. Worked with multiple sites spanning across the multiple continents. Managed teams up to 75. - 33+ years of experience in semiconductor design and management field. - Holds Patents (12 granted, 2 filed) and International Conference Publications (9). - Delivered invited talks to renowned academic institutes and IEEE-SSCS Forum. - Senior Member (80259417), IEEE and Solid State Circuits Society. - Adjunct Faculty at IIT, Jodhpur from 2023. Specialties: High Speed Serial Link (Physical Layer) design and Analog and Mixed Signal circuits, Mixed-Signal IP development team development and management.