Tanuj Jindal Email & Phone Number | Key strength: Immediate productivity, Inclination for efficiency improvement, Excellent Cross domain knowledge, debug and correlation capabilities. Technical expertise lies in Static Timing Analysis, Automation, Debug, Design Planning, Physical Design, Clocking and ability to correlate various aspects from RTL to GDS design for better PPA. Relevant Programming / Tools: C , C++ , TCL , Perl , Verilog , HSPICE , Design Compiler , PrimeTime , Fusion Compiler, ICC*, LEC , Virtuoso , Tango (Device / Std Cell Timing Analysis), Scarlet (RC extraction), Presto (Circuit simulation).

Tanuj Jindal

Key strength: Immediate productivity, Inclination for efficiency improvement, Excellent Cross domain...
Bengaluru, Karnataka, India

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Tanuj Jindal’s Email tanuj.jindal@intel.com

Tanuj Jindal’s Phone Numbers

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Tanuj Jindal’s Location Bengaluru, Karnataka, India

Tanuj Jindal’s Current Industry Intel

Tanuj Jindal’s Prior Industry Broadcom | Advanced Micro Devices | Texas Instruments

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Principal Engineer

2024-03-01 00:00:00 - Present

Senior Staff Engineer

2014-02-01 00:00:00 - 2014-08-01 00:00:00

Intern

2010-01-01 00:00:00 - 2010-05-01 00:00:00

Design Engineer

2006-07-01 00:00:00 - 2008-07-01 00:00:00

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Tanuj Jindal is a Key strength: Immediate productivity, Inclination for efficiency improvement, Excellent Cross domain knowledge, debug and correlation capabilities. Technical expertise lies in Static Timing Analysis, Automation, Debug, Design Planning, Physical Design, Clocking and ability to correlate various aspects from RTL to GDS design for better PPA. Relevant Programming / Tools: C , C++ , TCL , Perl , Verilog , HSPICE , Design Compiler , PrimeTime , Fusion Compiler, ICC*, LEC , Virtuoso , Tango (Device / Std Cell Timing Analysis), Scarlet (RC extraction), Presto (Circuit simulation).