Surendra Reddy Yanjarlapati Email & Phone Number | • Significant experience in ASIC Physical Design. - Netlist/Constraints Checks - Floor planning - Power Planning - Placement - Congestion and timing driven Placement and routing. - Timing optimization and signoff - CTS - Static Timing Analysis and signal integrity - Physical Verification(DRC,LVS and Antenna Fixes) -Worked on technology nodes 10nm, 14nm, 20nm, 28nm, 40nm, 45nm and 65nm.

Surendra Reddy Yanjarlapati

• Significant experience in ASIC Physical Design. - Netlist/Constraints Checks - Floor planning -...
Chandler, Arizona, United States

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Surendra Reddy Yanjarlapati’s Email surendra.yanjarlapati@intel.com

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Surendra Reddy Yanjarlapati’s Location Chandler, Arizona, United States

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Surendra Reddy Yanjarlapati’s Prior Industry Broadcom | Smartplay | Wipro

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Design Automation Engineer

2015-11-01 00:00:00 - Present

Engineer Sr Staff

2013-02-01 00:00:00 - 2015-11-01 00:00:00

Senior Engineer

2009-11-01 00:00:00 - 2013-02-01 00:00:00

Project Engineer

2006-09-01 00:00:00 - 2009-10-01 00:00:00

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Surendra Reddy Yanjarlapati is a • Significant experience in ASIC Physical Design. - Netlist/Constraints Checks - Floor planning - Power Planning - Placement - Congestion and timing driven Placement and routing. - Timing optimization and signoff - CTS - Static Timing Analysis and signal integrity - Physical Verification(DRC,LVS and Antenna Fixes) -Worked on technology nodes 10nm, 14nm, 20nm, 28nm, 40nm, 45nm and 65nm.