Shuting Xia
• Hands on experiences in ASIC design and verification of various successfully taped-out chips using...
Santa Clara, California, United States
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Shuting Xia’s Email shuting.xia@intel.com
Social Media
Shuting Xia’s Location Santa Clara, California, United States
Shuting Xia’s Current Industry
Shuting Xia’s Prior Industry Intel | Broadcom | University Of California Davis | Realsil Microelectronics
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Work Experience
Intel
Staff Design and Verification Engineer
2016-10-01 00:00:00 - 2018-05-01 00:00:00
Broadcom
Staff ASIC Design Engineer
2012-09-01 00:00:00 - 2016-09-01 00:00:00
University Of California Davis
Teaching Assistant
2010-01-01 00:00:00 - 2012-06-01 00:00:00
Realsil Microelectronics
Digital Design Engineer
2006-04-01 00:00:00 - 2009-03-01 00:00:00Skills
Languages
FAQ About Shuting Xia
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Shuting Xia is located at
Santa Clara, California, United States -
Shuting Xia is a • Hands on experiences in ASIC design and verification of various successfully taped-out chips using Verilog, SystemVerilog, Vera, VMM and UVM Methodology, Python/Perl • Domain knowledge on Ethernet, PCIE and Bus protocols • MS Degrees on both Computer Science and Electrical Engineering discipline and broad knowledge on both hardware and software • Fast learner and team player with good communication skills to work across multiple disciplines
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Shuting Xia currently works in the
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No Languages Available
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Shuting Xia has prior
experience in the following industries:
Intel | Broadcom | University Of California Davis | Realsil Microelectronics -
Shuting Xia has the following professional experience:
Intel | Broadcom | University Of California Davis | Realsil Microelectronics -
You can view Shuting Xia’s LinkedIn profile at LinkedIn URL
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Shuting Xia’s work email
addresses are
shuting.xia@intel.com -
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