Seong Yeol Mun Email & Phone Number | •Expertise in foundry CMOS process development & production: especially in 14FinFET •Extensive knowledge in device physics including LLE and process development through wide experience through the various kinds of devices: logic (mixed signal, RF), SRAM, DRAM, EEPROM embeded, CIS •Extensive experience & knowledge in SRAM including Vmin yield affected by SNM/WRM/Istdby or WRA/RA or periphery (WL driver/SA/write driver) and cell characterization and cell macro •Expert in MOSFET & Vmin margin simulation @cell level & @array level with VT/Vtmm/leakage path/resistance/WRA/RA/temperature for failure analysis or Vmin yield or HTOL improvements •Familiar with REL characterization method & concept and their improvements •Familiarity with circuit design concepts and their characteristics of basic standard cells like inv, nand, nor, AOI, OAI, etc and their simulation through schematics drawing using virtuoso •Knowledge & experience of RF/MS analog design constraints and dependence on key process parameters •Expertise in data analysis, DOE, and matrix/split lot design. •Experience in new product Introduction, characterization, process/product qualifications, manufacturing issues, and yield Improvement •Prior experience managing or interacting with external foundries, and qualifying new technologies for production. •Prior manager or group leader experience

Seong Yeol Mun

•Expertise in foundry CMOS process development & production: especially in 14FinFET •Extensive knowl...
United States

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Seong Yeol Mun’s Email smun@ovt.com

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Seong Yeol Mun’s Location United States

Seong Yeol Mun’s Current Industry Omnivision Technologies

Seong Yeol Mun’s Prior Industry Globalfoundries | Magnachip

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Senior Staff Engineer

2018-11-01 00:00:00 - Present

SMTS

2012-09-01 00:00:00 - 2018-10-01 00:00:00

Section Manager

1994-03-01 00:00:00 - 2008-08-01 00:00:00

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Seong Yeol Mun is a •Expertise in foundry CMOS process development & production: especially in 14FinFET •Extensive knowledge in device physics including LLE and process development through wide experience through the various kinds of devices: logic (mixed signal, RF), SRAM, DRAM, EEPROM embeded, CIS •Extensive experience & knowledge in SRAM including Vmin yield affected by SNM/WRM/Istdby or WRA/RA or periphery (WL driver/SA/write driver) and cell characterization and cell macro •Expert in MOSFET & Vmin margin simulation @cell level & @array level with VT/Vtmm/leakage path/resistance/WRA/RA/temperature for failure analysis or Vmin yield or HTOL improvements •Familiar with REL characterization method & concept and their improvements •Familiarity with circuit design concepts and their characteristics of basic standard cells like inv, nand, nor, AOI, OAI, etc and their simulation through schematics drawing using virtuoso •Knowledge & experience of RF/MS analog design constraints and dependence on key process parameters •Expertise in data analysis, DOE, and matrix/split lot design. •Experience in new product Introduction, characterization, process/product qualifications, manufacturing issues, and yield Improvement •Prior experience managing or interacting with external foundries, and qualifying new technologies for production. •Prior manager or group leader experience