Sanjay Pawar Email & Phone Number | * 9+ yrs experience in ASIC/SoC design and verification * Expertise in functional verification of AMD 64-bit microprocessor (Opteron) * Knowledge of x86 64-bit (AMD64) architecture, multiprocessor designs, ARM/MIPS based systems,AMBA/AHB/APB bus, caches, memory hierarchy, TLBs, peripheral interfaces such as HypterTransport (HT) & SDIO & DDR * Experience in RTL design & verification of systems with Embedded ARM/MIPS processors * Proficient in Verilog, x86 assembly, ARM assembly, Vera & Perl * Strong experience in block level, full chip verification, creating testplans, writing testbenches & verification flow development * Implemented self checking full chip regression flow with code coverage * Pioneered AMD Opteron first silicon debug project in Singapore * Debugged Opteron processor failures from simulation through silicon * Worked with system engineers to port tests to FPGA, silicon bringup & validation * Experience in working with AMD, Hewlett Packard and Philips Semiconductors teams in USA

Sanjay Pawar

* 9+ yrs experience in ASIC/SoC design and verification * Expertise in functional verification of AM...
Sunnyvale, California, United States

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Sanjay Pawar’s Email spawar@amd.com

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Sanjay Pawar’s Location Sunnyvale, California, United States

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Sanjay Pawar’s Prior Industry Nxp Semiconductors | Hewlett Packard | Advanced Micro Devices

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Senior Memeber of Technical Staff Engineer

2009-05-01 00:00:00 - Present

Chief Engineer, IC Design

2005-01-01 00:00:00 - 2008-06-01 00:00:00

Design Engineer II

2003-08-01 00:00:00 - 2005-01-01 00:00:00

Design Engineer

2000-10-01 00:00:00 - 2003-08-01 00:00:00

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Sanjay Pawar is a * 9+ yrs experience in ASIC/SoC design and verification * Expertise in functional verification of AMD 64-bit microprocessor (Opteron) * Knowledge of x86 64-bit (AMD64) architecture, multiprocessor designs, ARM/MIPS based systems,AMBA/AHB/APB bus, caches, memory hierarchy, TLBs, peripheral interfaces such as HypterTransport (HT) & SDIO & DDR * Experience in RTL design & verification of systems with Embedded ARM/MIPS processors * Proficient in Verilog, x86 assembly, ARM assembly, Vera & Perl * Strong experience in block level, full chip verification, creating testplans, writing testbenches & verification flow development * Implemented self checking full chip regression flow with code coverage * Pioneered AMD Opteron first silicon debug project in Singapore * Debugged Opteron processor failures from simulation through silicon * Worked with system engineers to port tests to FPGA, silicon bringup & validation * Experience in working with AMD, Hewlett Packard and Philips Semiconductors teams in USA