Sai Nikhil Email & Phone Number | 1. Good Knowledge on PCIE 3.0 and worked in Data Link Layer TX RTL implementation. 2. Good Knowledge on USB 3.0 and worked on RTL Integration of Protocol, Link, PHY layer and implemented tests for control transfer and bulk transfer. 3. Worked on USB 2.0 VIP, Implemented USB 2.0 registers using UVM RAL(Registers, Register block, adapter, predictor) and integrated with APB Agent, Implemented CRC5, CRC16, Control transfers logic, Reset, suspend, resume and speed negotiation in driver. 4. Worked on UNIPRO protocol, Implemented Test bench for DME Module, Implemented Registers using UVM RAL (Registers, Register block, Adapter, predictor) and integrated UVM RAL with AXI4 Lite VIP. Implemented DME Modular Level Testcases and RAL Functional coverage. Verified DME module twice in modular level verification and top level verification with 100% code and functional coverage and also implemented LM SAP interface assertions. Tools : VCS, Verdi, IMC, Cadence Xcelium, Simvision, Questa Sim. Languages : C, System Verilog, UVM, and Verilog Industrial Experience: 5 Years

Sai Nikhil

1. Good Knowledge on PCIE 3.0 and worked in Data Link Layer TX RTL implementation. 2. Good Knowledge...
Bengaluru, Karnataka, India

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Sai Nikhil’s Location Bengaluru, Karnataka, India

Sai Nikhil’s Current Industry Samsung Semiconductor

Sai Nikhil’s Prior Industry Sevitech Systems | Risetime Semiconductors | Ctrls Datacenters | Sirus Solar Power System

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Staff Engineer

2024-03-01 00:00:00 - Present

Senior Engineer

2019-11-01 00:00:00 - 2021-12-01 00:00:00

Asic Design And Verification Engineer

2018-06-01 00:00:00 - 2019-10-01 00:00:00

Trainee

2017-12-01 00:00:00 - 2018-02-01 00:00:00

Quality Department

2014-06-01 00:00:00 - 2014-12-01 00:00:00

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Sai Nikhil is a 1. Good Knowledge on PCIE 3.0 and worked in Data Link Layer TX RTL implementation. 2. Good Knowledge on USB 3.0 and worked on RTL Integration of Protocol, Link, PHY layer and implemented tests for control transfer and bulk transfer. 3. Worked on USB 2.0 VIP, Implemented USB 2.0 registers using UVM RAL(Registers, Register block, adapter, predictor) and integrated with APB Agent, Implemented CRC5, CRC16, Control transfers logic, Reset, suspend, resume and speed negotiation in driver. 4. Worked on UNIPRO protocol, Implemented Test bench for DME Module, Implemented Registers using UVM RAL (Registers, Register block, Adapter, predictor) and integrated UVM RAL with AXI4 Lite VIP. Implemented DME Modular Level Testcases and RAL Functional coverage. Verified DME module twice in modular level verification and top level verification with 100% code and functional coverage and also implemented LM SAP interface assertions. Tools : VCS, Verdi, IMC, Cadence Xcelium, Simvision, Questa Sim. Languages : C, System Verilog, UVM, and Verilog Industrial Experience: 5 Years

Sai Nikhil has prior
experience in the following industries:
Sevitech Systems | Risetime Semiconductors | Ctrls Datacenters | Sirus Solar Power System

Sai Nikhil has the following professional experience:
Samsung Semiconductor | Sevitech Systems | Risetime Semiconductors | Ctrls Datacenters | Sirus Solar Power System