Sagar Jariwala Email & Phone Number | Electrical Engineering Graduate Student majoring in Circuits and Systems with an acute interest in gaining hands-on experience in the field of ASIC/Physical Design and Verification/Validation. Looking for a challenging opportunity where I can utilize my skills and analytical ability to benefit the organization while willing to improve myself each day and strive towards excellence in my field of interest. SUMMARY OF SKILLS ● Strong knowledge of programming/scripting languages like Verilog, System Verilog, C/C++, Perl, Tcl, Shell. ● Strong knowledge of EDA tools like Cadence (Virtuoso Layout Suite, Schematic Editor, Encounter), Synopsys (Design Compiler, IC Compiler,SiliconSmart, HSPICE, Primetime, TetraMax), ModelSim IDE, and Xilinx ISE. ● Comprehensive knowledge of logic optimization, library characterization, RTL synthesis, floor planning, low power design techniques, multi clock domain designs and static timing analysis. ● Strong problem-solving skills, ability to work independently and take ownership of technical issues, good team player and strong writing/verbal communication skills. ● Having proficiency in : VLSI design, SOC, Physical Design, Synopsys, Logic design, Synthesis, Validation, Integrated Circuit system, Computer architecture, Scripting,Low Area, Low Power, Place and Route (P&R), Static Timing Analysis (STA) Strong coursework and hands on experience in following: ➤Technical: IC Design ➤Hardware Description/Verification Languages: Verilog, System Verilog ➤Scripting Languages: Perl, Tcl, Shell ➤Programming Languages: C, C++ ➤Tools: Cadence (Virtuoso, Spectre, SoC Encounter), Synopsys (HSPICE, Design Compiler, SiliconSmart, HSPICE, Primetime, TetraMax), Xilinx ISE, ModelSim, MATLAB

Sagar Jariwala

Electrical Engineering Graduate Student majoring in Circuits and Systems with an acute interest in g...
San Diego, California, United States

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Sagar Jariwala’s Email sjariwala@qualcomm.com

Sagar Jariwala’s Phone Numbers +1 858-651-****

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Sagar Jariwala’s Location San Diego, California, United States

Sagar Jariwala’s Current Industry Qualcomm

Sagar Jariwala’s Prior Industry Microchip Technology | Scalable Systems Research Labs

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Work Experience

Qualcomm

Senior Low Power Design Enginner

2021-05-01 00:00:00 - Present

Microchip Technology

Design Engineer - II

2018-04-01 00:00:00 - 2021-05-01 00:00:00

Scalable Systems Research Labs

ASIC Design Intern

2017-06-01 00:00:00 - 2018-04-01 00:00:00

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FAQ About Sagar Jariwala

Sagar Jariwala is located at
San Diego, California, United States

Sagar Jariwala is a Electrical Engineering Graduate Student majoring in Circuits and Systems with an acute interest in gaining hands-on experience in the field of ASIC/Physical Design and Verification/Validation. Looking for a challenging opportunity where I can utilize my skills and analytical ability to benefit the organization while willing to improve myself each day and strive towards excellence in my field of interest. SUMMARY OF SKILLS ● Strong knowledge of programming/scripting languages like Verilog, System Verilog, C/C++, Perl, Tcl, Shell. ● Strong knowledge of EDA tools like Cadence (Virtuoso Layout Suite, Schematic Editor, Encounter), Synopsys (Design Compiler, IC Compiler,SiliconSmart, HSPICE, Primetime, TetraMax), ModelSim IDE, and Xilinx ISE. ● Comprehensive knowledge of logic optimization, library characterization, RTL synthesis, floor planning, low power design techniques, multi clock domain designs and static timing analysis. ● Strong problem-solving skills, ability to work independently and take ownership of technical issues, good team player and strong writing/verbal communication skills. ● Having proficiency in : VLSI design, SOC, Physical Design, Synopsys, Logic design, Synthesis, Validation, Integrated Circuit system, Computer architecture, Scripting,Low Area, Low Power, Place and Route (P&R), Static Timing Analysis (STA) Strong coursework and hands on experience in following: ➤Technical: IC Design ➤Hardware Description/Verification Languages: Verilog, System Verilog ➤Scripting Languages: Perl, Tcl, Shell ➤Programming Languages: C, C++ ➤Tools: Cadence (Virtuoso, Spectre, SoC Encounter), Synopsys (HSPICE, Design Compiler, SiliconSmart, HSPICE, Primetime, TetraMax), Xilinx ISE, ModelSim, MATLAB