Sachin Kirdat Email & Phone Number | Have a strong understanding of ASIC design flow. Digital design skills. Verilog/SV RTL design, Good understanding of verification concepts, functional verification, post gate simulations. Analog mix signal verification & VMM based verification, UPF simulations. Good knowledge of power analysis for full-chip with HSIM sims. experience with Formality checks and spyglass cheks Mix signal verification with HSIM+VSIM. Good understanding of CMOS technology & standard cell library format. Spice check (ERC) for multi Voltage design and reliability checks with spice checks get required reviews and documentation done for stream out procedure. Experience with silicon debug & solving customer issue Has exposure to 45nm/65nm tech. Project documentation & management Guiding & training jr team members on their tasks. Specialties: ASIC design, Digital Design, CMOS tech, Verilog, Functional Verification, Formal Verification, Post layout verification, Full chip IPD current measurement, ERC/ Spice Check ( for multi Voltage domain crossing checks), Mixed-signal simulation with Vsim-HSIM (Co-sim)

Sachin Kirdat

Have a strong understanding of ASIC design flow. Digital design skills. Verilog/SV RTL design, Good...
Bengaluru, Bengaluru, India

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Sachin Kirdat’s Location Bengaluru, Bengaluru, India

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Sachin Kirdat’s Prior Industry Cadence Design Systems | Semiconductor Complex | Monitor Tech Pune

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Engineering Manager

Present

Member Of Tech Staff

2004-09-01 00:00:00 - 2006-02-01 00:00:00

Design Engr

2001-09-01 00:00:00 - 2004-09-01 00:00:00

Engineer

2000-06-01 00:00:00 - 2001-02-01 00:00:00

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Sachin Kirdat is a Have a strong understanding of ASIC design flow. Digital design skills. Verilog/SV RTL design, Good understanding of verification concepts, functional verification, post gate simulations. Analog mix signal verification & VMM based verification, UPF simulations. Good knowledge of power analysis for full-chip with HSIM sims. experience with Formality checks and spyglass cheks Mix signal verification with HSIM+VSIM. Good understanding of CMOS technology & standard cell library format. Spice check (ERC) for multi Voltage design and reliability checks with spice checks get required reviews and documentation done for stream out procedure. Experience with silicon debug & solving customer issue Has exposure to 45nm/65nm tech. Project documentation & management Guiding & training jr team members on their tasks. Specialties: ASIC design, Digital Design, CMOS tech, Verilog, Functional Verification, Formal Verification, Post layout verification, Full chip IPD current measurement, ERC/ Spice Check ( for multi Voltage domain crossing checks), Mixed-signal simulation with Vsim-HSIM (Co-sim)