Rupesh Shelar
Software developer, IC designer, and a researcher. Passionate about algorithms; invented and impleme...
Hillsboro, Oregon, United States
*50 free lookup(s) per month.
No credit card required.
Rupesh Shelar’s Email rshelar@cadence.com
Social Media
Rupesh Shelar’s Location Hillsboro, Oregon, United States
Rupesh Shelar’s Current Industry Intel
Rupesh Shelar’s Prior Industry Cadence Design Systems | Synopsys | Lsi | Strategic Cad Labs Intel | Silicon Automation Systems Bangalore
Not the Rupesh Shelar you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience
Intel
Senior Staff Design Engineer
2023-11-01 00:00:00 - Present
Cadence Design Systems
Software Architect
2020-07-01 00:00:00 - 2023-04-01 00:00:00
Synopsys
Senior Staff R&D Engineer
2016-10-01 00:00:00 - 2020-07-01 00:00:00
Lsi
Principal Engineer
2012-09-01 00:00:00 - 2014-09-01 00:00:00
Strategic Cad Labs Intel
Grdaute Technical Intern
2003-06-01 00:00:00 - 2003-09-01 00:00:00
Silicon Automation Systems Bangalore
Software Engineer
1999-03-01 00:00:00 - 2000-05-01 00:00:00Skills
Languages
FAQ About Rupesh Shelar
-
Rupesh Shelar is located at
Hillsboro, Oregon, United States -
Rupesh Shelar is a Software developer, IC designer, and a researcher. Passionate about algorithms; invented and implemented those for CAD tools. - Hands on development for large complex software stack for emulation, prototyping platforms (Zebu, Protium) that use Xilinx FPGAs - Have hands on experience on SoC designs for phone, automotive infotainment, solid state drive controllers and for microprocessors (Core i7, Atom) in the areas of clock distribution, power analysis, physical and circuit design in technologies ranging from 65 nm - 10 nm. - Invented clock tree synthesis related algorithms impacting multiple microprocessor generations across multiple product lines at Intel. - Authored/co-authored a book (published by Springer), a book chapter, 20 refereed journal (TCAD, TVLSI) and conference papers. - Have served on technical program committees of ISPD 2010, 2011. - Reviewer for TCAD, TVLSI, DAC, ICCAD, and for Cadence Innovation Conference 22, 23 - Reviewed SRC funding proposals and have initiated/mentored a research project with Texas A&M University. - Gave invited talks at universities such as UT Austin, IIT (Mumbai). - IEEE Senior Member since 2011.
-
Rupesh Shelar currently works in the Intel |
-
No Languages Available
-
Rupesh Shelar has prior
experience in the following industries:
Cadence Design Systems | Synopsys | Lsi | Strategic Cad Labs Intel | Silicon Automation Systems Bangalore -
Rupesh Shelar has the following professional experience:
Intel | Cadence Design Systems | Synopsys | Lsi | Strategic Cad Labs Intel | Silicon Automation Systems Bangalore -
You can view Rupesh Shelar’s LinkedIn profile at LinkedIn URL
-
Rupesh Shelar’s work email
addresses are
rshelar@cadence.com -
Intel |
People you may be interested in
-
Brian Naccarelli
-
Rachel Anyetei
-
Louise Corris
-
Rani Elhajjar
-
David Steele
Senior Director of Marketing Acquisition
Joined PwC in September 2019 as a part of their...
A committed and passionate care home manager with a focus...
Author of Composite Structures: Effects of Defects by Wiley. https://www.wiley.com/en-us/Composite+Structures%3A+Effects+of+Defects-p-9781118997727...
Technical Support for North America, Trainer and mentor to team...
