Roopak Vasa Email & Phone Number | As a Sr R&D Engineer 2 at Synopsys, I have more than 12 years of experience in the semiconductor field, specializing in embedded memory design. I have a strong background in bit cell analysis, process entitlement, write and read margin, timing race margin analysis, sense amplifier analysis, level shifter analysis, verilog equivalence checks, timing, leakage, and power characterization, and fullRC instance at speed simulations. I have contributed to the successful release of several memory compilers and instances for various technologies and applications, such as Intel 16 cold cmos LTLT, N7 HS1PRF Auto, GF12, and SMIC12. I have also developed innovative tools and utilities to improve the margin, reliability, and performance of memory circuits. I have been recognized for my leadership, mentorship, and innovation, winning the runner-up in the Ace Award 2023 and being nominated for the Ace Award 2022. I am passionate about delivering high-quality solutions that meet the needs of our customers and partners.

Roopak Vasa

As a Sr R&D Engineer 2 at Synopsys, I have more than 12 years of experience in the semiconductor fie...
Hyderabad, Telangana, India

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Roopak Vasa’s Location Hyderabad, Telangana, India

Roopak Vasa’s Current Industry Micron Technology

Roopak Vasa’s Prior Industry Synopsys | Invecas | Stmicroelectronics | St Microelectronics

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Principal Engineer Memory Circuit Design Verification

2024-04-01 00:00:00 - Present

R & D Engineer, Sr 2

2021-11-01 00:00:00 - 2024-04-01 00:00:00

Mts

2018-04-01 00:00:00 - 2020-02-01 00:00:00

Memory Design Engineer(Contractor)

2012-05-01 00:00:00 - 2014-02-01 00:00:00

Trainee

2011-07-01 00:00:00 - 2012-04-01 00:00:00

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Roopak Vasa is a As a Sr R&D Engineer 2 at Synopsys, I have more than 12 years of experience in the semiconductor field, specializing in embedded memory design. I have a strong background in bit cell analysis, process entitlement, write and read margin, timing race margin analysis, sense amplifier analysis, level shifter analysis, verilog equivalence checks, timing, leakage, and power characterization, and fullRC instance at speed simulations. I have contributed to the successful release of several memory compilers and instances for various technologies and applications, such as Intel 16 cold cmos LTLT, N7 HS1PRF Auto, GF12, and SMIC12. I have also developed innovative tools and utilities to improve the margin, reliability, and performance of memory circuits. I have been recognized for my leadership, mentorship, and innovation, winning the runner-up in the Ace Award 2023 and being nominated for the Ace Award 2022. I am passionate about delivering high-quality solutions that meet the needs of our customers and partners.