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Ritesh Singh

 Hands on experience in Verilog, System Verilog, C.  Hands on Experience in using Verification Met...
Hyderabad, Telangana, India

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Work Experience

Microchip Technology

Principal Engineer

Present

Cyient

Senior Verification Engineer

2017-09-01 00:00:00 - 2021-04-01 00:00:00

Synaptics

Asic Engineer

2012-04-01 00:00:00 - 2017-09-01 00:00:00

Ip Core Solutions

Engineer Trainee

2011-05-01 00:00:00 - 2012-05-01 00:00:00

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