Ranjeet Kumar Jha Email & Phone Number | 1. DDR4 Memory System (ThunderX2, ThunderX3 ARM server processor) : # Pre-silicon functional verification, post-silicon validation of DDR4 based memory controller/PHY; Led the firmware development of the memory driver, DIMM AVL methodology, margin tool development. # Worked with HPC/Hyper-scale customers to achieve server class performance of DDR4 memory system in production. #Achieved 1-DPC/2-DPC DDR4-3200 RDIMM stability on ref platforms with 8 memory channels per node spread across two nodes in ThunderX3-A0 with ~310 GB/S stream nos. 2. Sub-system coherency verification (Thunder X3 ARM server processor) : Subsystem consists of CPU’s back-end, the coherent interconnect, tile-based coherency controller and L3, DDR memories, the IO’s spread over multi nodes 3. Tech Lead for Load-Store, Memory Management, Secondary Cache blocks verification (Thunder X4 ARM server)

Ranjeet Kumar Jha

1. DDR4 Memory System (ThunderX2, ThunderX3 ARM server processor) : # Pre-silicon functional verifi...
Santa Clara, California, United States

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Ranjeet Kumar Jha’s Email ranjeet.jha@cavium.com

Ranjeet Kumar Jha’s Phone Numbers +1 408-943-****

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Ranjeet Kumar Jha’s Location Santa Clara, California, United States

Ranjeet Kumar Jha’s Current Industry Intel

Ranjeet Kumar Jha’s Prior Industry Cavium | Netlogic Microsystems | Raza Microelectronics | Nvidia | Motorola

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Sr Lead - PreSI hardware design verification

2021-01-01 00:00:00 - Present

Principal Engineer

2016-12-01 00:00:00 - 2021-01-01 00:00:00

Masters Engineer/Sr Principal Engineer

2010-10-01 00:00:00 - 2016-12-01 00:00:00

Chip Design Verification consultant

2007-10-01 00:00:00 - 2010-03-01 00:00:00

Chip Design Verification Consultant

2005-01-01 00:00:00 - 2007-01-01 00:00:00

Sr Design Engineer - VLSI

1999-11-01 00:00:00 - 2005-06-01 00:00:00

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Ranjeet Kumar Jha is a 1. DDR4 Memory System (ThunderX2, ThunderX3 ARM server processor) : # Pre-silicon functional verification, post-silicon validation of DDR4 based memory controller/PHY; Led the firmware development of the memory driver, DIMM AVL methodology, margin tool development. # Worked with HPC/Hyper-scale customers to achieve server class performance of DDR4 memory system in production. #Achieved 1-DPC/2-DPC DDR4-3200 RDIMM stability on ref platforms with 8 memory channels per node spread across two nodes in ThunderX3-A0 with ~310 GB/S stream nos. 2. Sub-system coherency verification (Thunder X3 ARM server processor) : Subsystem consists of CPU’s back-end, the coherent interconnect, tile-based coherency controller and L3, DDR memories, the IO’s spread over multi nodes 3. Tech Lead for Load-Store, Memory Management, Secondary Cache blocks verification (Thunder X4 ARM server)