Ram Puralasetty Email & Phone Number | 13 years of experience in Full chip/sub system/IP level ASIC Soc Design, RTL Integration and RTL coding, Functional Verification, coverage Analysis, Gate level simulations & Post Silicon validation & debugging, vector generation & testing on ATE.

Ram Puralasetty

13 years of experience in Full chip/sub system/IP level ASIC Soc Design, RTL Integration and RTL co...
Leander, Texas, United States

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Ram Puralasetty’s Email ram.puralasetty@intel.com

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Ram Puralasetty’s Location Leander, Texas, United States

Ram Puralasetty’s Current Industry Intel

Ram Puralasetty’s Prior Industry Sasken Communication Technologies | Qualcomm | Qualcore Hyderabad

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Soc Design Verification Engineer

2016-01-01T00:00:00.000Z - Present

Lead Engineer - ICdesign

2006-09-01T00:00:00.000Z - 2015-12-01T00:00:00.000Z

consultant

2009-08-01T00:00:00.000Z - 2012-03-01T00:00:00.000Z

ASIC-Engineer

2005-06-01T00:00:00.000Z - 2006-08-01T00:00:00.000Z

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Ram Puralasetty is a 13 years of experience in Full chip/sub system/IP level ASIC Soc Design, RTL Integration and RTL coding, Functional Verification, coverage Analysis, Gate level simulations & Post Silicon validation & debugging, vector generation & testing on ATE.