Raj Hiremath Email & Phone Number | 1. Seeking a responsible & challenging position to utilize my skills and abilities in the circuit design field, while being self-motivated, energetic, resourceful, innovative and flexible. I will contribute my maximum potential. 2. Skilled in CMOS, Circuit Design, deep know how of bitcell, memory margin and overall design flow. Experience of working on low power, High speed, high Density, pseudo dual port, ROM and dual port compilers compilers. 3. Good amount of knowledge on PDK development using parameterised cells using cadence SKILL. 4. Proficent knowledge on Development of internal EDA tool using languages like c, shell, tcl, SKILL etc. 5. Good knowledge on memory architecture and memory tiling for the technologies 28nm, 40nm using place and route tool ITESS, Memory canvas, Cubic compiler. 5. Working knowledge on memory compilers for technologies 5nm, 7nm, 10nm, 14nm, 28nm and 40nm. 6. Good understanding DRC and LVS of memories and standard cells for technologies 16nm finFET, 28nm and 40nm, 7. Good knowledge on standard cells automation for different drive strengths using language SKILL for 16nm finFET technology. 8. Enough knowledge on Synthesis flow using the synopsys and cadence tools.

Raj Hiremath

1. Seeking a responsible & challenging position to utilize my skills and abilities in the circuit de...
India

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Raj Hiremath’s Location India

Raj Hiremath’s Current Industry Broadcom

Raj Hiremath’s Prior Industry Samsung Electronics | Dxcorr Design | Lsi

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Staff Engineer

2019-06-01 00:00:00 - Present

Technical Lead

2015-04-01 00:00:00 - 2019-06-01 00:00:00

Senior Member Of Technical Staff

2010-07-01 00:00:00 - 2015-04-01 00:00:00

Intern

2007-07-01 00:00:00 - 2008-01-01 00:00:00

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Raj Hiremath is a 1. Seeking a responsible & challenging position to utilize my skills and abilities in the circuit design field, while being self-motivated, energetic, resourceful, innovative and flexible. I will contribute my maximum potential. 2. Skilled in CMOS, Circuit Design, deep know how of bitcell, memory margin and overall design flow. Experience of working on low power, High speed, high Density, pseudo dual port, ROM and dual port compilers compilers. 3. Good amount of knowledge on PDK development using parameterised cells using cadence SKILL. 4. Proficent knowledge on Development of internal EDA tool using languages like c, shell, tcl, SKILL etc. 5. Good knowledge on memory architecture and memory tiling for the technologies 28nm, 40nm using place and route tool ITESS, Memory canvas, Cubic compiler. 5. Working knowledge on memory compilers for technologies 5nm, 7nm, 10nm, 14nm, 28nm and 40nm. 6. Good understanding DRC and LVS of memories and standard cells for technologies 16nm finFET, 28nm and 40nm, 7. Good knowledge on standard cells automation for different drive strengths using language SKILL for 16nm finFET technology. 8. Enough knowledge on Synthesis flow using the synopsys and cadence tools.