Priyanka Phatak Email & Phone Number | OBJECTIVE Aspiring for a challenging career that would complement my Educational, Technical and Organizational skills. Industry Experience: 11 Years 10 Months Work Experience: 1. SOC DFT Engineer in Intel Technologies (Sept.2019-till present): Worked on various DFT techniques, RTL integration, validation, ATPG pattern generation and GLS debugs. 2. Staff Engineer at Samsung Semiconductors India R&D (March 2014-Sept. 2019): Worked on MBIST insertion, verification, GLS, and post silicon debugs. 3. System Engineer at Infosys Ltd. (May 2011 - Feb. 2014) Tool Skill Set: • EDA Tools : DVE, VCS, NCSIM, SimVision, Tessent LV, Tessent Shell, Tetramax, VTRAN Vector Conversion tool. • Scripting Language : TCL/Tk, PERL, Shell scripting. • Hardware Language : Verilog HDL, System Verilog, OVM/UVM • DFT Techniques : MBIST Insertion, MBIST verification, ATPG Pattern Generation, SCAN GLS, LBIST Verification, IJTAG, Post Silicon Debug

Priyanka Phatak

OBJECTIVE Aspiring for a challenging career that would complement my Educational, Technical and Org...
Intel, NO 17, India

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Priyanka Phatak’s Email priyanka.phatak@intel.com

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Priyanka Phatak’s Location Intel, NO 17, India

Priyanka Phatak’s Current Industry Intel

Priyanka Phatak’s Prior Industry Samsung R And D Institute India Bangalore | Cisco | Infosys

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Soc Dft Engineer

2018-09-01 00:00:00 - Present

Staff Engineer

2014-03-01 00:00:00 - 2018-09-01 00:00:00

Contract Engineer Asic Dft-Us

2011-10-01 00:00:00 - 2014-02-01 00:00:00

System Engineer Trainee

2011-05-01 00:00:00 - 2011-09-01 00:00:00

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Priyanka Phatak is a OBJECTIVE Aspiring for a challenging career that would complement my Educational, Technical and Organizational skills. Industry Experience: 11 Years 10 Months Work Experience: 1. SOC DFT Engineer in Intel Technologies (Sept.2019-till present): Worked on various DFT techniques, RTL integration, validation, ATPG pattern generation and GLS debugs. 2. Staff Engineer at Samsung Semiconductors India R&D (March 2014-Sept. 2019): Worked on MBIST insertion, verification, GLS, and post silicon debugs. 3. System Engineer at Infosys Ltd. (May 2011 - Feb. 2014) Tool Skill Set: • EDA Tools : DVE, VCS, NCSIM, SimVision, Tessent LV, Tessent Shell, Tetramax, VTRAN Vector Conversion tool. • Scripting Language : TCL/Tk, PERL, Shell scripting. • Hardware Language : Verilog HDL, System Verilog, OVM/UVM • DFT Techniques : MBIST Insertion, MBIST verification, ATPG Pattern Generation, SCAN GLS, LBIST Verification, IJTAG, Post Silicon Debug