Prince George Email & Phone Number | Working for Broadcom as an ASIC design engineer with 12 years of experience. Primary responsibility is STA with other skills as below. Specialties: Static Timing Analysis (STA), Statistical Static Timing Analysis (SSTA), At speed structural test timing (ASST), sign-off timing for functional and scan modes, Understanding the test modes ( Shift, Capture, MBIST, LOES, TDF etc) and writing the constraints for them, DDR timing closure, constraints validation-GCA, Power supply noise analysis and mitigation, signal integrity, coupling noise analysis and mitigation, TCL, Statistical Timing Clossure, Assertions/constraints development and qualification, formality, formal verification, Low power design (UPF2.0), VCLP. Scripting Language: Perl, TCL, CShell.

Prince George

Working for Broadcom as an ASIC design engineer with 12 years of experience. Primary responsibilit...
Bengaluru, Karnataka, India

*50 free lookup(s) per month.

Prince George’s Phone Numbers

Get PRINCE’s Phone Number (For Free)

Social Media

Prince George’s Location Bengaluru, Karnataka, India

Prince George’s Current Industry Marvell Technology

Prince George’s Prior Industry Broadcom | Lsi An Avago Technologies | Pmc Sierra | Ibm

Find accurate emails & phone numbers for over 700M professionals.

Graphics Hardware Engineer

Present

Principal Engineer

2023-06-01 00:00:00 - Present

Sta Lead

2017-04-01 00:00:00 - 2020-04-01 00:00:00

System-On-Chip Design Engineer

2014-11-01 00:00:00 - 2017-04-01 00:00:00

Timing Lead

2014-06-01 00:00:00 - 2014-11-01 00:00:00

Asic Design Center Engineer

2006-07-01 00:00:00 - 2014-06-01 00:00:00

No Skills Available

No Languages Available

Prince George is a Working for Broadcom as an ASIC design engineer with 12 years of experience. Primary responsibility is STA with other skills as below. Specialties: Static Timing Analysis (STA), Statistical Static Timing Analysis (SSTA), At speed structural test timing (ASST), sign-off timing for functional and scan modes, Understanding the test modes ( Shift, Capture, MBIST, LOES, TDF etc) and writing the constraints for them, DDR timing closure, constraints validation-GCA, Power supply noise analysis and mitigation, signal integrity, coupling noise analysis and mitigation, TCL, Statistical Timing Clossure, Assertions/constraints development and qualification, formality, formal verification, Low power design (UPF2.0), VCLP. Scripting Language: Perl, TCL, CShell.