Praveen Vadlamudi Email & Phone Number | • Currently working in AMD as Member of Technical Staff in Cores Tool Flow Methodology team to enable Physical Design flow, DFT specification and flow setup , LEC with formality and conformal for all core designs. • Worked on Physical Design (RTL to GDSII ) implementation for intel 4nm, 7nm, 10nm, 14nm and 22nm and TSMC 3nm , 4nm and 5nm. • Worked on Logic Synthesis, Floor planning, Power planning, placement, CTS, routing, fill and all physical design sign off flows • Worked on Low power design closure and associated sign off flows • Worked on Physical verification (DRC/LVS/Antenna.etc) • Worked on Reliability verification (EM/IR drop etc) • Worked on standard cell specification definition for MIG IPs from 22nm to 4nm intel process nodes.

Praveen Vadlamudi

• Currently working in AMD as Member of Technical Staff in Cores Tool Flow Methodology team to enabl...
Bengaluru, Karnataka, India

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Praveen Vadlamudi’s Email pvadlamudi@amd.com

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Praveen Vadlamudi’s Location Bengaluru, Karnataka, India

Praveen Vadlamudi’s Current Industry Intel

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Physical Design Engineer Lead

2024-03-01 00:00:00 - Present

Member Of Technical Staff

2022-09-01 00:00:00 - 2024-03-01 00:00:00

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Praveen Vadlamudi is a • Currently working in AMD as Member of Technical Staff in Cores Tool Flow Methodology team to enable Physical Design flow, DFT specification and flow setup , LEC with formality and conformal for all core designs. • Worked on Physical Design (RTL to GDSII ) implementation for intel 4nm, 7nm, 10nm, 14nm and 22nm and TSMC 3nm , 4nm and 5nm. • Worked on Logic Synthesis, Floor planning, Power planning, placement, CTS, routing, fill and all physical design sign off flows • Worked on Low power design closure and associated sign off flows • Worked on Physical verification (DRC/LVS/Antenna.etc) • Worked on Reliability verification (EM/IR drop etc) • Worked on standard cell specification definition for MIG IPs from 22nm to 4nm intel process nodes.