Prajwala Rani Dandigi Email & Phone Number | Physical design engineer with 7+ years of experience, working on RTL2GDS flow. Ø Worked on block-level Synthesis, Low Power checks, Floorplanning, Placement, CTS, Route, and Timing Analysis. Ø Handled multiple tasks effectively. Ø Worked on 14nm, 10nm, 7nm, 3nm Technology nodes. MULTIPLE tapeouts. Ø Reliability checks and fixing. Ø Block level Timing fixes and interface timing fixes. Ø Good knowledge in STA (Static Timing Analysis) Ø DRC/LVS debugging and resolving at PD end. Ø Rigorous ECO cycles (timing/logical) to close on time. Ø Scripting Skills TCL. · EDA tools: DC-Innovus, fusion compiler, ICC2,, Prime Time (for timing analysis), Calibre for PV checks.

Prajwala Rani Dandigi

Physical design engineer with 7+ years of experience, working on RTL2GDS flow. Ø Worked on block-lev...
Bengaluru, Bengaluru, India

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Prajwala Rani Dandigi’s Email pd@einfochips.com

Prajwala Rani Dandigi’s Phone Numbers +1 408-496-****

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Prajwala Rani Dandigi’s Location Bengaluru, Bengaluru, India

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Senior PD Engineer

2020-02-01 00:00:00 - Present

PD Engineer

2018-04-01 00:00:00 - 2020-02-01 00:00:00

Physical Design Engineer

2016-06-01 00:00:00 - 2018-03-01 00:00:00

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Prajwala Rani Dandigi is a Physical design engineer with 7+ years of experience, working on RTL2GDS flow. Ø Worked on block-level Synthesis, Low Power checks, Floorplanning, Placement, CTS, Route, and Timing Analysis. Ø Handled multiple tasks effectively. Ø Worked on 14nm, 10nm, 7nm, 3nm Technology nodes. MULTIPLE tapeouts. Ø Reliability checks and fixing. Ø Block level Timing fixes and interface timing fixes. Ø Good knowledge in STA (Static Timing Analysis) Ø DRC/LVS debugging and resolving at PD end. Ø Rigorous ECO cycles (timing/logical) to close on time. Ø Scripting Skills TCL. · EDA tools: DC-Innovus, fusion compiler, ICC2,, Prime Time (for timing analysis), Calibre for PV checks.