Pradeep Tiwari Email & Phone Number | Here is brief summary of my work experience. I have total 10 years of experience. ~7.5 years of IO Design Experience. ************************************************* Currently working on IO Designs in 14nm FinFet technology. (i) Worked on JEDEC Compliant Bidirectional GPIO Design (General Purpose IO) for Foundry Technologies in 350nm, 180nm, 130nm, 32nm,14nm (ii) Worked on both current based and impedance based CMOS driver design with Multiple Impedance & Multiple Slew Programmable IO. (iii) Worked on the receiver design with Hysteresis Block. (iv) Worked on high Voltage tolerant receiver IO design. (v) Worked on differential driver design operating at 1 GHz in 22nm. Hands on experience of IBIS model generation & Validation Hands on experience with Layout design for IO's. Exposure to IO characterization, Physical Verification, LEF generation. Understanding of ESD, Latch-up, Electromigration. Worked with design teams spread across multiple geographies. Tools Used : Cadence ADEXL for Schematic Design/Spectre simulation. Cadence Assura/Mentor Calibre for DRC/LVS Physical Verification. NCX for IO characterization. Spectre MDL for running spectre simulation. ************************************************* 2 .5 Years of Experience in DRC/LVS verification and update of existing designs. Migrating existing designs from one process technology to another process. *************************************************

Pradeep Tiwari

Here is brief summary of my work experience. I have total 10 years of experience. ~7.5 years of IO...
Bengaluru, Karnataka, India

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Pradeep Tiwari’s Location Bengaluru, Karnataka, India

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Pradeep Tiwari’s Prior Industry Ust Global | Cypress Semiconductor | Globalfoundries | Ibm

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Manager, A andMs Circuit Design

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Manager, A&Ms Circuit Design

2019-06-01 00:00:00 - Present

Io Circuit Designer At Ust Global, Malaysia

2017-01-01 00:00:00 - 2018-05-01 00:00:00

Staff Electrical Design Engineer

2016-03-01 00:00:00 - 2016-12-01 00:00:00

Io Circuit Designer

2015-07-01 00:00:00 - 2016-03-01 00:00:00

Staff R & D Engineer

2007-09-01 00:00:00 - 2015-06-01 00:00:00

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Pradeep Tiwari is a Here is brief summary of my work experience. I have total 10 years of experience. ~7.5 years of IO Design Experience. ************************************************* Currently working on IO Designs in 14nm FinFet technology. (i) Worked on JEDEC Compliant Bidirectional GPIO Design (General Purpose IO) for Foundry Technologies in 350nm, 180nm, 130nm, 32nm,14nm (ii) Worked on both current based and impedance based CMOS driver design with Multiple Impedance & Multiple Slew Programmable IO. (iii) Worked on the receiver design with Hysteresis Block. (iv) Worked on high Voltage tolerant receiver IO design. (v) Worked on differential driver design operating at 1 GHz in 22nm. Hands on experience of IBIS model generation & Validation Hands on experience with Layout design for IO's. Exposure to IO characterization, Physical Verification, LEF generation. Understanding of ESD, Latch-up, Electromigration. Worked with design teams spread across multiple geographies. Tools Used : Cadence ADEXL for Schematic Design/Spectre simulation. Cadence Assura/Mentor Calibre for DRC/LVS Physical Verification. NCX for IO characterization. Spectre MDL for running spectre simulation. ************************************************* 2 .5 Years of Experience in DRC/LVS verification and update of existing designs. Migrating existing designs from one process technology to another process. *************************************************