Perceval Coudrain Email & Phone Number | Senior 3D Integration Engineer Strong background in multi-scale 3D integration, from transistors to packaging, with a large practical experience in advanced 3D prototyping: -TSV last process for WLP of image sensors and Power Amplifiers -TSV Middle integration for face-to-face digital/analog partitionning -TSV Middle integration for face-to-back Wide I/O memory on Logic stacking -Monolithic 3D integration for advanced miniaturized CMOS pixels Expertise in thin film deposition (CVD, PVD, PLD), with 10 years of experience in CMOS / MEMS processing. Extended knowledge in miniaturized Active Pixel Sensors technologies (low noise pixels, backside illumination (BSI), Wafer Level Package (WLP)). Active participation on European/French collaborative projects (NANO2012, OSEO, FP6, ANR, Catrene). Expert for ANR project evaluation. Occasionally teaching on Advanced CMOS Image Sensors technology.

Perceval Coudrain

Senior 3D Integration Engineer Strong background in multi-scale 3D integration, from transistors to...
Grenoble, Auvergne-Rhone-Alpes, France

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Perceval Coudrain’s Email perceval.coudrain@st.com

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Perceval Coudrain’s Location Grenoble, Auvergne-Rhone-Alpes, France

Perceval Coudrain’s Current Industry Cea Commissariat Alenergie Atomique Et Aux Energies Alternatives

Perceval Coudrain’s Prior Industry Stmicroelectronics | National Tsing Hua University

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Advanced Packaging & 3d Integration

2018-05-01 00:00:00 - Present

More Than Moore - Advanced Projects Management

2016-02-01 00:00:00 - 2018-05-01 00:00:00

R&D Internship

2001-02-01 00:00:00 - 2001-08-01 00:00:00

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Perceval Coudrain is a Senior 3D Integration Engineer Strong background in multi-scale 3D integration, from transistors to packaging, with a large practical experience in advanced 3D prototyping: -TSV last process for WLP of image sensors and Power Amplifiers -TSV Middle integration for face-to-face digital/analog partitionning -TSV Middle integration for face-to-back Wide I/O memory on Logic stacking -Monolithic 3D integration for advanced miniaturized CMOS pixels Expertise in thin film deposition (CVD, PVD, PLD), with 10 years of experience in CMOS / MEMS processing. Extended knowledge in miniaturized Active Pixel Sensors technologies (low noise pixels, backside illumination (BSI), Wafer Level Package (WLP)). Active participation on European/French collaborative projects (NANO2012, OSEO, FP6, ANR, Catrene). Expert for ANR project evaluation. Occasionally teaching on Advanced CMOS Image Sensors technology.

Perceval Coudrain currently works in the Cea Commissariat Alenergie Atomique Et Aux Energies Alternatives |

Perceval Coudrain has prior
experience in the following industries:
Stmicroelectronics | National Tsing Hua University

Perceval Coudrain has the following professional experience:
Cea Commissariat Alenergie Atomique Et Aux Energies Alternatives | Stmicroelectronics | National Tsing Hua University