Pawan Khare Email & Phone Number | ASIC Verification: SOC and IP Level, Gate Level Simulations Languages: Verilog, System Verilog, OVM, UVM Methodologies, Specman, C Protocols: PCI Express 1.1 and 2.0, DDR1 and DDR2, AMBA AXI/AHB/APB, SPI, I2C, UART Scripting: PERL, Shell, TCL, Python

Pawan Khare

ASIC Verification: SOC and IP Level, Gate Level Simulations Languages: Verilog, System Verilog, OVM,...
Bangalore Rural, Karnataka, India

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Pawan Khare’s Email pkhare@broadcom.com

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Pawan Khare’s Location Bangalore Rural, Karnataka, India

Pawan Khare’s Current Industry

Pawan Khare’s Prior Industry Broadcom Research | Broadcom India Research | Conexant Systems | Cypress Semiconductor

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Master Engineer

Present

Engineer Principal- Ic Design

2015-03-01 00:00:00 - 2018-10-01 00:00:00

Engineer- Sr. Staff Ic-Design

2013-08-01 00:00:00 - 2015-02-01 00:00:00

Lead Design Engineer - Verification

2008-02-01 00:00:00 - 2013-08-01 00:00:00

Sr. Cad Engineer

2006-11-01 00:00:00 - 2007-08-01 00:00:00

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Pawan Khare is a ASIC Verification: SOC and IP Level, Gate Level Simulations Languages: Verilog, System Verilog, OVM, UVM Methodologies, Specman, C Protocols: PCI Express 1.1 and 2.0, DDR1 and DDR2, AMBA AXI/AHB/APB, SPI, I2C, UART Scripting: PERL, Shell, TCL, Python

Pawan Khare has prior
experience in the following industries:
Broadcom Research | Broadcom India Research | Conexant Systems | Cypress Semiconductor

Pawan Khare has the following professional experience:
Broadcom | Broadcom Research | Broadcom India Research | Conexant Systems | Cypress Semiconductor