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Patrick Erich

Digital design, AISC, FPGA, VHDL, Verilog, SystemVerilog, Python
Delft, Delft, Netherlands

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Work Experience

Innatera

Staff Digital Design Engineer

2024-03-01T00:00:00.000Z - Present

Sabb At Ical

Interest explorer

2022-01-01T00:00:00.000Z - 2023-02-01T00:00:00.000Z

Systematic Design

Senior Digital Design Engineer

2004-07-01T00:00:00.000Z - 2021-12-01T00:00:00.000Z

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