Nitin Tiwari Email & Phone Number | Senior engineering manager with high motivation and skill to provide silicon efficient and first time right IP/SoC Layout Solutions. Summary of Experience • 18+ years of well-rounded experience of Physical Design execution of Digital Sub systems, Custom Analog IPs and Full Chip Layouts. • Strong People management skills. Managing teams since 2016. • Execution Strength in Full Chip Floor-planning, Bump planning & routing, ESD planning - implementation - signoff, RV execution – signoff, LV execution - signoff • Physical Design Execution Lead for IPs like Crypto QAT (Quick Assist Technology) accelerator IP for Server SoC, Mustang Mesa etc • Strong stakeholder and cross-geo execution management skills. • Hiring, and building Physical Design teams • Contract workforce management – Vendor selection, RUNDA creation, onboarding, project execution. • Excellent team leader/mentor with excellent communication, interpersonal skills, and strong work ethic. I have a Master of Science degree in VLSI and Computer Architectures from the University of Tennessee at Knoxville & a Bachelors degree in Electrical and Electronics from Manipal Institute of Technology. My long term goals are to deliver cutting edge IPs and SoC designs & be a full chip layout architect.

Nitin Tiwari

Senior engineering manager with high motivation and skill to provide silicon efficient and first ti...
Bengaluru, Karnataka, India

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Nitin Tiwari’s Email nitin.tiwari@intel.com

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Nitin Tiwari’s Location Bengaluru, Karnataka, India

Nitin Tiwari’s Current Industry Intel

Nitin Tiwari’s Prior Industry Kpit Cummins Infosystems

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Physical SoC Design Engineer

2011-07-01T00:00:00.000Z - Present

Technical Lead, Analog and Mixed Signals group

2005-06-01T00:00:00.000Z - 2011-01-01T00:00:00.000Z

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Nitin Tiwari is a Senior engineering manager with high motivation and skill to provide silicon efficient and first time right IP/SoC Layout Solutions. Summary of Experience • 18+ years of well-rounded experience of Physical Design execution of Digital Sub systems, Custom Analog IPs and Full Chip Layouts. • Strong People management skills. Managing teams since 2016. • Execution Strength in Full Chip Floor-planning, Bump planning & routing, ESD planning - implementation - signoff, RV execution – signoff, LV execution - signoff • Physical Design Execution Lead for IPs like Crypto QAT (Quick Assist Technology) accelerator IP for Server SoC, Mustang Mesa etc • Strong stakeholder and cross-geo execution management skills. • Hiring, and building Physical Design teams • Contract workforce management – Vendor selection, RUNDA creation, onboarding, project execution. • Excellent team leader/mentor with excellent communication, interpersonal skills, and strong work ethic. I have a Master of Science degree in VLSI and Computer Architectures from the University of Tennessee at Knoxville & a Bachelors degree in Electrical and Electronics from Manipal Institute of Technology. My long term goals are to deliver cutting edge IPs and SoC designs & be a full chip layout architect.