Mark Steigerwald Email & Phone Number | Experienced in netlist to GDS creation (logic synthesis, floorplanning and partitioning, place and route, clock tree synthesis, power delivery, timing closure, signal integrity analysis, DRC/LVS), full chip integration and tapeout, SRAM/register file/CAM design, silicon debug, and CMOS layout design.

Mark Steigerwald

Experienced in netlist to GDS creation (logic synthesis, floorplanning and partitioning, place and r...
San Jose, California, United States

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Calibre Applications Engineering

2019-03-01 00:00:00 - Present

Director of Consulting Services

2017-03-01 00:00:00 - 2019-03-01 00:00:00

Full Chip Lead Designer, IC Design Engineering

2012-02-01 00:00:00 - 2016-12-01 00:00:00

Full Chip Lead Designer

2010-07-01 00:00:00 - 2012-02-01 00:00:00

Physical Design Lead, Hardware Development

2010-02-01 00:00:00 - 2010-06-01 00:00:00

Physical Design Lead

2002-04-01 00:00:00 - 2010-02-01 00:00:00

Design engineer

2000-02-01 00:00:00 - 2002-04-01 00:00:00

Circuit Design Engineer

1995-03-01 00:00:00 - 2000-02-01 00:00:00

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Mark Steigerwald is a Experienced in netlist to GDS creation (logic synthesis, floorplanning and partitioning, place and route, clock tree synthesis, power delivery, timing closure, signal integrity analysis, DRC/LVS), full chip integration and tapeout, SRAM/register file/CAM design, silicon debug, and CMOS layout design.

Mark Steigerwald has prior
experience in the following industries:
Sintegra | Broadcom | Netlogic Microsystems | Oracle | Sun Microsystems | Nexsi Systems | Intel

Mark Steigerwald has the following professional experience:
Mentor Graphics | Sintegra | Broadcom | Netlogic Microsystems | Oracle | Sun Microsystems | Nexsi Systems | Intel