Loi Phan Email & Phone Number | • Extensive experience in RF measurements such as modulation accuracy/SNR, phase noise, impedance matching, noise figure, linearity, spurious emission, spectrum, frequency versus time • Solid knowledge and experience in debugging of mm-Wave beamforming transceivers, PLLs, clock synthesizers, wireless receivers (GPS, DTV), transceivers/SoC (single-chip multi-band FDD LTE/HSPA+/EDGE and TDD LTE/TD-SCDMA) • Extensive experience in designing evaluation boards and production multi-site boards • Proficient in developing test methodology for multi-site production of RFIC • Proven results as Application engineer and IC Validation engineer • Proficient with RF and Timing test equipment such as vector network analyzer, phase noise analyzer, spectrum analyzer, signal generator, noise meter • Exceptional analytical and problem solving skills, strong data analysis skills

Loi Phan

• Extensive experience in RF measurements such as modulation accuracy/SNR, phase noise, impedance ma...
Phoenix, Phoenix, United States

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Loi Phan’s Email loi.phan@idt.com

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Loi Phan’s Location Phoenix, Phoenix, United States

Loi Phan’s Current Industry Idt Integrated Device Technology

Loi Phan’s Prior Industry Microchip Technology | Nvidia | Icera Semiconductor | Texas Instruments | National Biodynamic Laboratory

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Principal Application Engineer

2017-07-01T00:00:00.000Z - Present

Principal Application Engineer

2015-07-01T00:00:00.000Z - 2017-07-01T00:00:00.000Z

Senior RF Engineer

2011-06-01T00:00:00.000Z - 2015-06-01T00:00:00.000Z

RF Product/Test Engineer

2008-09-01T00:00:00.000Z - 2011-10-01T00:00:00.000Z

RF Product/Test Engineer

2006-03-01T00:00:00.000Z - 2008-09-01T00:00:00.000Z

Engineering Intern

1998-05-01T00:00:00.000Z - 1998-08-01T00:00:00.000Z

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Loi Phan is a • Extensive experience in RF measurements such as modulation accuracy/SNR, phase noise, impedance matching, noise figure, linearity, spurious emission, spectrum, frequency versus time • Solid knowledge and experience in debugging of mm-Wave beamforming transceivers, PLLs, clock synthesizers, wireless receivers (GPS, DTV), transceivers/SoC (single-chip multi-band FDD LTE/HSPA+/EDGE and TDD LTE/TD-SCDMA) • Extensive experience in designing evaluation boards and production multi-site boards • Proficient in developing test methodology for multi-site production of RFIC • Proven results as Application engineer and IC Validation engineer • Proficient with RF and Timing test equipment such as vector network analyzer, phase noise analyzer, spectrum analyzer, signal generator, noise meter • Exceptional analytical and problem solving skills, strong data analysis skills

Loi Phan has prior
experience in the following industries:
Microchip Technology | Nvidia | Icera Semiconductor | Texas Instruments | National Biodynamic Laboratory

Loi Phan has the following professional experience:
Idt Integrated Device Technology | Microchip Technology | Nvidia | Icera Semiconductor | Texas Instruments | National Biodynamic Laboratory