Kalman Pelhos Email & Phone Number | I am currently a senior productivity engineering manager at Intel, Santa Clara, CA, working on non-volatile memory development. Primary responsibilities include global cross-functional team leadership in developing productivity solutions, improving yield, reducing cost for 3DNAND production, interfacing with suppliers, as well as Intel Technology Development and High Volume Manufacturing operations. Previously, I was a staff process engineer at Lam Research, Etch Product Development, Dielectric Etch Process C&F group in Fremont, CA, working on various pathfinding projects ranging from cryogenic etch, new etch chemistries, liner assisted etch, development of advanced metrology techniques. Before that, I was a senior staff engineer at Seagate Technology in Fremont, CA. My project was R&D in patterned magnetic media - specifically, pursuing an ion implantation based approach. While I was responsible for the fabrication of prototype patterned disks (pattern hard mask, implant, strip, clean) and delivered demo disks built into drives, I also interacted with major equipment vendors on outlining a mass-production capable pilot line, establishing technical specs, cost, throughput and yield targets. Previously, I was a senior research manager at Seagate in Pittsburgh, PA, where I was working on HAMR or heat assisted magnetic recording, building prototype heads for this novel recording technology, developing new materials and processes, relying on my expertise is in thin film deposition (PVD, IBD, PECVD) of metals and optical quality dielectrics mostly for waveguide applications, mirrors, anti-reflective coatings, etc., as well as vacuum and/or plasma based dry etch (RIE, IBE, RIBE) of the same films. I also have a strong background is surface analysis (XPS, Auger, SEM, LEED, LEEM, TPD, STM, AFM).

Kalman Pelhos

I am currently a senior productivity engineering manager at Intel, Santa Clara, CA, working on non-v...
Santa Clara, California, United States

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Kalman Pelhos’s Email kalman.pelhos@lamresearch.com

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Kalman Pelhos’s Location Santa Clara, California, United States

Kalman Pelhos’s Current Industry Mattson Technology

Kalman Pelhos’s Prior Industry Intel | Lam Research | Seagate Technology | Bell Laboratories

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Work Experience

Mattson Technology

DMTS

2024-01-01 00:00:00 - Present

Intel

Senior Engineering Manager

2022-01-01 00:00:00 - 2024-01-01 00:00:00

Lam Research

Staff Process Engineer

2012-03-01 00:00:00 - 2018-10-01 00:00:00

Seagate Technology

Senior Staff Engineer

2009-03-01 00:00:00 - 2012-03-01 00:00:00

Bell Laboratories

MTS

2000-01-01 00:00:00 - 2001-09-01 00:00:00

Skills

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Languages

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FAQ About Kalman Pelhos

Kalman Pelhos is located at
Santa Clara, California, United States

Kalman Pelhos is a I am currently a senior productivity engineering manager at Intel, Santa Clara, CA, working on non-volatile memory development. Primary responsibilities include global cross-functional team leadership in developing productivity solutions, improving yield, reducing cost for 3DNAND production, interfacing with suppliers, as well as Intel Technology Development and High Volume Manufacturing operations. Previously, I was a staff process engineer at Lam Research, Etch Product Development, Dielectric Etch Process C&F group in Fremont, CA, working on various pathfinding projects ranging from cryogenic etch, new etch chemistries, liner assisted etch, development of advanced metrology techniques. Before that, I was a senior staff engineer at Seagate Technology in Fremont, CA. My project was R&D in patterned magnetic media - specifically, pursuing an ion implantation based approach. While I was responsible for the fabrication of prototype patterned disks (pattern hard mask, implant, strip, clean) and delivered demo disks built into drives, I also interacted with major equipment vendors on outlining a mass-production capable pilot line, establishing technical specs, cost, throughput and yield targets. Previously, I was a senior research manager at Seagate in Pittsburgh, PA, where I was working on HAMR or heat assisted magnetic recording, building prototype heads for this novel recording technology, developing new materials and processes, relying on my expertise is in thin film deposition (PVD, IBD, PECVD) of metals and optical quality dielectrics mostly for waveguide applications, mirrors, anti-reflective coatings, etc., as well as vacuum and/or plasma based dry etch (RIE, IBE, RIBE) of the same films. I also have a strong background is surface analysis (XPS, Auger, SEM, LEED, LEEM, TPD, STM, AFM).