Joseph Benjamin Email & Phone Number | IP Design Verification for next-gen FPGAs - Development of AMBA AXI4 BFM DFx logic validation of next gen Intel SoCs Post-Silicon validation of Graphics processing unit - functional validation of integrated GPU including test creation and execution for various GPU features and power management. Functional verification and debug of ASIC. Develop test sequences and debug regression failures with waveforms and log files to achieve tape-in timeline targets. GPU Performance Verification of Adreno GPUs - Analysis and improvement of next-generation Adreno GPU architecture based on benchmarks and peak performance tests. Post Silicon Validation R&D Engineer at IBM India Pvt. Ltd. - Exerciser tools development for IBM PowerPC server processors' architecture validation. GPS based mobile embedded system using an 8-bit ATMEL micro-controller to receive GPS coordinates and transmit them as SMS messages. MS in EEE. Concentration in Computer Architecture, Digital Design, VLSI and embedded systems exposure. Digital Logic Design, CMOS and VLSI, Advanced Computer Architecture and Static Timing Analysis. Verilog HDL coding, testing and synthesis, CMOS and VLSI technology knowledge, computer architecture. C, C++, with exposure to PERL scripting, Java and Visual Basic.

Joseph Benjamin

IP Design Verification for next-gen FPGAs - Development of AMBA AXI4 BFM DFx logic validation of ne...
Bayan Lepas, Penang, Malaysia

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Joseph Benjamin’s Email jbenjamin@qualcomm.com

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Joseph Benjamin’s Location Bayan Lepas, Penang, Malaysia

Joseph Benjamin’s Current Industry Intel

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Work Experience

Intel

Fpga Ip Software Development Engineer

2023-02-01 00:00:00 - Present

Ust Global

Verification Engineer

2017-05-01 00:00:00 - 2020-08-01 00:00:00

Mindlance Technologies

Engineer

2015-04-01 00:00:00 - 2017-05-01 00:00:00

Global Banking And Finance Review

Business Consultant

2015-01-01 00:00:00 - 2015-03-01 00:00:00

John 316 Mission Foundation

Program Manager

2014-09-01 00:00:00 - 2014-12-01 00:00:00

Ibm

Post Silicon Validation Engineer

2010-12-01 00:00:00 - 2014-03-01 00:00:00

Intel Corporation Mmdc

Component Design Engineer - Intern

2008-02-01 00:00:00 - 2008-08-01 00:00:00

Skills

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Languages

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FAQ About Joseph Benjamin

Joseph Benjamin is located at
Bayan Lepas, Penang, Malaysia

Joseph Benjamin is a IP Design Verification for next-gen FPGAs - Development of AMBA AXI4 BFM DFx logic validation of next gen Intel SoCs Post-Silicon validation of Graphics processing unit - functional validation of integrated GPU including test creation and execution for various GPU features and power management. Functional verification and debug of ASIC. Develop test sequences and debug regression failures with waveforms and log files to achieve tape-in timeline targets. GPU Performance Verification of Adreno GPUs - Analysis and improvement of next-generation Adreno GPU architecture based on benchmarks and peak performance tests. Post Silicon Validation R&D Engineer at IBM India Pvt. Ltd. - Exerciser tools development for IBM PowerPC server processors' architecture validation. GPS based mobile embedded system using an 8-bit ATMEL micro-controller to receive GPS coordinates and transmit them as SMS messages. MS in EEE. Concentration in Computer Architecture, Digital Design, VLSI and embedded systems exposure. Digital Logic Design, CMOS and VLSI, Advanced Computer Architecture and Static Timing Analysis. Verilog HDL coding, testing and synthesis, CMOS and VLSI technology knowledge, computer architecture. C, C++, with exposure to PERL scripting, Java and Visual Basic.

Joseph Benjamin currently works in the Intel |

No Languages Available

Joseph Benjamin has prior
experience in the following industries:
Ust Global | Mindlance Technologies | Global Banking And Finance Review | John 316 Mission Foundation | Ibm | Intel Corporation Mmdc

Joseph Benjamin has the following professional experience:
Intel | Ust Global | Mindlance Technologies | Global Banking And Finance Review | John 316 Mission Foundation | Ibm | Intel Corporation Mmdc

You can view Joseph Benjamin’s LinkedIn profile at LinkedIn URL

Joseph Benjamin’s work email
addresses are
jbenjamin@qualcomm.com

Intel |

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