Jeffrey Claudio Email & Phone Number | A graduate with some background in Verilog / SystemVerilog, RTL Design, Design Verification, and Physical Design. I have had the opportunity to design analog/digital circuits, translate them to physical layouts using Cadence Virtuoso, convert algorithms to state machines which where verified in ModelSim and synthesized in Quartus Prime. I have also been exposed to the UVM testing environment that makes use of a scoreboard and other verification classes along with assertions and functional coverage. With the experience I hold, I hope to start working on RTL Design/Verification on ICs to aid in developing next generation processors!

Jeffrey Claudio

A graduate with some background in Verilog / SystemVerilog, RTL Design, Design Verification, and Phy...
238 Haversham Way, Davenport, United States

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Jeffrey Claudio’s Email eng@leidos.com

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Jeffrey Claudio’s Location 238 Haversham Way, Davenport, United States

Jeffrey Claudio’s Current Industry Northrop Grumman

Jeffrey Claudio’s Prior Industry Leidos | Vans A Vf

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ASIC Design Engineer

2023-05-01 00:00:00 - Present

Distribution Design Engineer

2021-09-01 00:00:00 - 2023-05-01 00:00:00

Sales Associate

2015-07-01 00:00:00 - 2018-10-01 00:00:00

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Jeffrey Claudio is a A graduate with some background in Verilog / SystemVerilog, RTL Design, Design Verification, and Physical Design. I have had the opportunity to design analog/digital circuits, translate them to physical layouts using Cadence Virtuoso, convert algorithms to state machines which where verified in ModelSim and synthesized in Quartus Prime. I have also been exposed to the UVM testing environment that makes use of a scoreboard and other verification classes along with assertions and functional coverage. With the experience I hold, I hope to start working on RTL Design/Verification on ICs to aid in developing next generation processors!