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James Branvold


Ottawa, Ontario, Canada

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Work Experience

Career Break

Retirement

2022-03-01 00:00:00 - Present

Fidus Systems

Senior ASIC Verification Engineer

2019-01-01 00:00:00 - 2022-04-01 00:00:00

Branvold Consulting

Owner

2014-02-01 00:00:00 - 2022-04-01 00:00:00

Ciena

Senior ASIC Verification Engineer

2014-02-01 00:00:00 - 2022-04-01 00:00:00

Ross Video

Senior ASIC Verification Engineer

2016-09-01 00:00:00 - 2019-01-01 00:00:00

Coveloz

Senior FPGA Verification Engineer

2014-02-01 00:00:00 - 2016-09-01 00:00:00

Flextronics

Senior ASIC/FPGA Design Engineer

2013-02-01 00:00:00 - 2014-01-01 00:00:00

Edgewater Computer Systems

Senior ASIC/FPGA Designer

2005-05-01 00:00:00 - 2008-04-01 00:00:00

Ralus

Senior FPGA Designer

2003-06-01 00:00:00 - 2005-05-01 00:00:00

Accelight Network

Senior FPGA Designer

2000-08-01 00:00:00 - 2002-12-01 00:00:00

Tundra Semiconductor

Senior ASIC Designer

1994-08-01 00:00:00 - 2000-07-01 00:00:00

Newbridge Microsystems

Coop ASIC Verification

1993-09-01 00:00:00 - 1993-12-01 00:00:00

Bell Northern Research

Coop Hardware Designer

1993-01-01 00:00:00 - 1993-04-01 00:00:00

Beline Manufacturing

Coop Hardware Designer

1992-05-01 00:00:00 - 1992-08-01 00:00:00

Esso

Coop Software Designer

1991-09-01 00:00:00 - 1991-12-01 00:00:00

Skills

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Languages

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