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Hussain Neralwala

Have worked multiple times across the SOC chip cycle starting from micro-architecture to RTL design,...
Bengaluru, Karnataka, India

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Work Experience

Google

ASIC RTL Design Lead

2022-10-01 00:00:00 - Present

Intel

Logic Design Lead

2019-10-01 00:00:00 - 2022-10-01 00:00:00

Broadcom

IC Design Engineer

2014-07-01 00:00:00 - 2017-06-01 00:00:00

Marvell Semiconductor

ASIC Design Engineer

2012-12-01 00:00:00 - 2014-07-01 00:00:00

Tejas Networks

R&D Engineer

2010-07-01 00:00:00 - 2012-12-01 00:00:00

Iit Bombay

Research scholar

2008-01-01 00:00:00 - 2010-09-01 00:00:00

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