Hina Mushir Email & Phone Number | 24 years of solid experience in the semiconductor industry with successful tape outs in different technology nodes, having good in depth knowledge of various domains of IC design and expertise in - Logic Diagnosis for yield enhancement and test time reductions to identify systematic yield detractors leading into acceleration of volume production with Synopsys Yield Explorer. - Silicon validation (Yield, Characterization, Maturity, Life Test) from new silicon bring up to qualification leading to yield ramp-up of various digital IPs (Memories/Stdcells/PMBs) across various technology nodes, process and fabs. - Design for test methodologies, to increase coverage and quality - Generation of ATPG pattern including cell aware patterns with Synopsys and functional testbench - Conversion of test benches to various ATEs (Verigy, Teradyne etc) using TestInSight - All aspects of netlist to GDSII flow : Physical design domain - Floor planning, Power routing & analysis, backend placement & routing, CTGen (Clock Tree), Timing Signoff Closure (STA), LVS & DRC for various technology nodes.

Hina Mushir

24 years of solid experience in the semiconductor industry with successful tape outs in different t...
New Delhi, New Delhi, India

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Hina Mushir’s Email hina.mushir@st.com

Hina Mushir’s Phone Numbers +63 49 523 ****

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Hina Mushir’s Location New Delhi, New Delhi, India

Hina Mushir’s Current Industry

Hina Mushir’s Prior Industry St Microelectronics | Stmicroelectronics

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Senior Staff Engineer

2012-01-01 00:00:00 - 2023-01-01 00:00:00

Staff Engineer

1999-01-01 00:00:00 - 2012-01-01 00:00:00

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Hina Mushir is a 24 years of solid experience in the semiconductor industry with successful tape outs in different technology nodes, having good in depth knowledge of various domains of IC design and expertise in - Logic Diagnosis for yield enhancement and test time reductions to identify systematic yield detractors leading into acceleration of volume production with Synopsys Yield Explorer. - Silicon validation (Yield, Characterization, Maturity, Life Test) from new silicon bring up to qualification leading to yield ramp-up of various digital IPs (Memories/Stdcells/PMBs) across various technology nodes, process and fabs. - Design for test methodologies, to increase coverage and quality - Generation of ATPG pattern including cell aware patterns with Synopsys and functional testbench - Conversion of test benches to various ATEs (Verigy, Teradyne etc) using TestInSight - All aspects of netlist to GDSII flow : Physical design domain - Floor planning, Power routing & analysis, backend placement & routing, CTGen (Clock Tree), Timing Signoff Closure (STA), LVS & DRC for various technology nodes.