Heta Shah Email & Phone Number | - Worked as physical design engineer for complex & high-performance latch-based core design (high frequency 4Ghz design) on multiple Intel technology nodes like 14nm, 10nm & 7nm. - Lead the convergence of partition-based design for Graphics SOC design on 7nm Intel technology. - Worked on multiple PPA activities like DP2RLS & BigRLS for core design. - Good knowledge on Data path design & RLS designs flows for the industry standard tools like DC, ICC2 & Fusion compiler. - Worked and knowledge on Placement, Clock Tree Synthesis, and Routing (PNR), Optimization, Static Timing Analysis (STA), Formal Equivalence Verification, DRC and Sign Off flows. - Lead the central activities for multiple blocks library refresh and timing convergence. - Implementation of different low power methodologies for power reduction. - ECO implementation and Layout quality fixes.

Heta Shah

- Worked as physical design engineer for complex & high-performance latch-based core design (high fr...
Intel, NO 17, India

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Physical Design Engineer

2023-12-01 00:00:00 - Present

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Heta Shah is a - Worked as physical design engineer for complex & high-performance latch-based core design (high frequency 4Ghz design) on multiple Intel technology nodes like 14nm, 10nm & 7nm. - Lead the convergence of partition-based design for Graphics SOC design on 7nm Intel technology. - Worked on multiple PPA activities like DP2RLS & BigRLS for core design. - Good knowledge on Data path design & RLS designs flows for the industry standard tools like DC, ICC2 & Fusion compiler. - Worked and knowledge on Placement, Clock Tree Synthesis, and Routing (PNR), Optimization, Static Timing Analysis (STA), Formal Equivalence Verification, DRC and Sign Off flows. - Lead the central activities for multiple blocks library refresh and timing convergence. - Implementation of different low power methodologies for power reduction. - ECO implementation and Layout quality fixes.