Harish Venkumahanti Email & Phone Number | Over 14 years of experience in Chip Design and Implementation involving - Physical Design, Chip Top level and Block Level floor planning,placement,Place and Route,Clock Tree Synthesis,Signal Integrity,Timing closure. - Implementation Lead responsibilities in Physical design and Timing closure. - Good ASIC Exposure from RTL Design,Verification,Synthesis, STA to Physical Design Implementation. -Expert in Timing Analysis and Timing Closure and highly experienced in developing and owning full chip Timing Constraints for a complex Multi clock SoCs. -Successful tapeout experience of multiple complex chips at 28nm, 45nm , 65nm, 90nm. -Strong core competency in Timing closure from RTL Design to Tape out. -Proficient in Scripting and Automation in tcl, shell,dbget/dbSet.

Harish Venkumahanti

Over 14 years of experience in Chip Design and Implementation involving - Physical Design, Chip Top...
Sunnyvale, California, United States

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Harish Venkumahanti’s Email hvenkumahanti@apple.com

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Harish Venkumahanti’s Location Sunnyvale, California, United States

Harish Venkumahanti’s Current Industry Apple

Harish Venkumahanti’s Prior Industry Sandisk | Wipro Technologies

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Senior Physical Design Timing Engineer

2014-03-01 00:00:00 - Present

Senior Staff (Physical Design Lead) Engineer

2009-12-01 00:00:00 - 2014-03-01 00:00:00

Asic Physical Design Consultant

2005-10-01 00:00:00 - 2010-01-01 00:00:00

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Harish Venkumahanti is a Over 14 years of experience in Chip Design and Implementation involving - Physical Design, Chip Top level and Block Level floor planning,placement,Place and Route,Clock Tree Synthesis,Signal Integrity,Timing closure. - Implementation Lead responsibilities in Physical design and Timing closure. - Good ASIC Exposure from RTL Design,Verification,Synthesis, STA to Physical Design Implementation. -Expert in Timing Analysis and Timing Closure and highly experienced in developing and owning full chip Timing Constraints for a complex Multi clock SoCs. -Successful tapeout experience of multiple complex chips at 28nm, 45nm , 65nm, 90nm. -Strong core competency in Timing closure from RTL Design to Tape out. -Proficient in Scripting and Automation in tcl, shell,dbget/dbSet.