Harika Renduchintala Email & Phone Number | Graduate student in ASIC/CMOS design and UVM verification from San Jose State University (SJSU). My specialization includes Very Large Scale Integrated Circuits( VLSI), Digital System Design and Synthesis, Computer Architecture, ASIC CMOS Design, SoC Design and verification, Hardware Description Languages. • 2+ years of experience coding in Verilog and ASIC/CMOS Design. • 1 year of experience building Universal Verification Methodology (UVM) Testbenches to determine if the DUT works as expected, Functional and Code coverage. • 1 year of experience on Neural Networks for digit recognition and designing and optimized Neural Network model using pruning and Bit-accurate techniques and Computer Architecture. • Extensive knowledge of Verilog verification, Static Timing Analysis (STA), Verilog modeling and EDA tools. • A good understanding of RTL Description, Floor Planning, Placement, and Routing. • Knowledge of ASIC Design flow, Simulation, and Synthesis of RTL. Skill Set: • EDA/CAD/ Tools: Synopsys VCS, Quartus II 13.0, Design Compiler, MATLAB, Xilinx ISE, Cadence Virtuoso, Xilinx, Pspice • Languages: Verilog, VHDL, System Verilog, C, SQL • Operating Systems: Linux, Unix, Windows • Scripting Languages: Python, Perl • Bus Protocols: SPI, I2C, PCIe, APB, AHB

Harika Renduchintala

Graduate student in ASIC/CMOS design and UVM verification from San Jose State University (SJSU). My...
Austin, Texas, United States

*50 free lookup(s) per month.

Harika Renduchintala’s Email hrenduchintala@cadence.com

Harika Renduchintala’s Phone Numbers

Get HARIKA’s Phone Number (For Free)

Social Media

Harika Renduchintala’s Location Austin, Texas, United States

Harika Renduchintala’s Current Industry Intel

Harika Renduchintala’s Prior Industry Cadence Design Systems | Synopsys | Bharat Sanchar Nigam

Find accurate emails & phone numbers for over 700M professionals.

Design Automation Engineer

2022-06-01 00:00:00 - Present

Sr Application Engineer

2021-02-01 00:00:00 - 2022-06-01 00:00:00

Application Engineer II

2018-11-01 00:00:00 - 2021-01-01 00:00:00

Summer Intern

2014-05-01 00:00:00 - 2014-08-01 00:00:00

No Skills Available

No Languages Available

Harika Renduchintala is a Graduate student in ASIC/CMOS design and UVM verification from San Jose State University (SJSU). My specialization includes Very Large Scale Integrated Circuits( VLSI), Digital System Design and Synthesis, Computer Architecture, ASIC CMOS Design, SoC Design and verification, Hardware Description Languages. • 2+ years of experience coding in Verilog and ASIC/CMOS Design. • 1 year of experience building Universal Verification Methodology (UVM) Testbenches to determine if the DUT works as expected, Functional and Code coverage. • 1 year of experience on Neural Networks for digit recognition and designing and optimized Neural Network model using pruning and Bit-accurate techniques and Computer Architecture. • Extensive knowledge of Verilog verification, Static Timing Analysis (STA), Verilog modeling and EDA tools. • A good understanding of RTL Description, Floor Planning, Placement, and Routing. • Knowledge of ASIC Design flow, Simulation, and Synthesis of RTL. Skill Set: • EDA/CAD/ Tools: Synopsys VCS, Quartus II 13.0, Design Compiler, MATLAB, Xilinx ISE, Cadence Virtuoso, Xilinx, Pspice • Languages: Verilog, VHDL, System Verilog, C, SQL • Operating Systems: Linux, Unix, Windows • Scripting Languages: Python, Perl • Bus Protocols: SPI, I2C, PCIe, APB, AHB