Grant Martin Email & Phone Number | Grant Martin retired in October 2023. Grant was a consultant for three years. He was a Distinguished Engineer from 2013 to 2020 in the Tensilica R&D group of Cadence Design Systems, and prior to that, Chief Scientist at Tensilica for 9 years.He also worked for Burroughs in Scotland, Nortel/BNR in Canada, and Cadence Design Systems, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978. As a consultant, Grant worked with d-Matrix and other large and small companies in the areas of DSP and configurable processor architecture and design. This work has included market and technical analysis of RISC-V based processors and other configurable processors; detailed design of vector processors for embedded AI applications; and ISA architecting of new DSPs. Grant is a co-author or co-editor of ten books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and system-level design, including the first book on SoC design published in Russian. He was co-chair of the DAC Technical Programme Committee for Methods for 2005 and 2006. His particular areas of interest include DSPs and configurable processors, functional safety solutions including Software Test Libraries and for AI/ML on neural net accelerators, RISC-V instruction set architectures and applications, system-level design, IP-based design of system-on-chip, platform-based design, application-specific instruction set processors, and embedded software. He is a co-editor of the Springer series on embedded systems. Grant is a Senior Member of the IEEE. Specialties: configurable processors, Tensilica, Xtensa, TiE, RISC-V, Electronic Design Automation, System-on-Chip Design methodology, System-Level Design, Platform Based Design, ESL, EDA, SoC, functional safety and cybersecurity of embedded systems (automotive), including functional safety architectures for AI/ML, automated DSP development methodology, Software Test Libraries (STLs) for configurable processors and DSPs

Grant Martin

Grant Martin retired in October 2023. Grant was a consultant for three years. He was a Distinguishe...
Pleasanton, California, United States

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Grant Martin’s Location Pleasanton, California, United States

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Work Experience

None

Retired

2023-10-01 00:00:00 - Present

Self Employed

Consultant, DSPs and Configurable Processors

2020-12-01 00:00:00 - 2023-09-01 00:00:00

Cadence Design Systems

Distinguished Engineer

2013-04-01 00:00:00 - 2020-12-01 00:00:00

Tensilica

Chief Scientist

2004-03-01 00:00:00 - 2013-04-01 00:00:00

Northern Telecom

Senior Manager

1994-01-01 00:00:00 - 1994-12-01 00:00:00

Bell Northern Research

Member of Scientific Staff, Manager, Senior Manager

1984-06-01 00:00:00 - 1993-12-01 00:00:00

Burroughs Machines

Associate to Senior Systems Engineer and Section Head

1978-10-01 00:00:00 - 1984-06-01 00:00:00

Skills

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Languages

No Languages Available

FAQ About Grant Martin

Grant Martin is located at
Pleasanton, California, United States

Grant Martin is a Grant Martin retired in October 2023. Grant was a consultant for three years. He was a Distinguished Engineer from 2013 to 2020 in the Tensilica R&D group of Cadence Design Systems, and prior to that, Chief Scientist at Tensilica for 9 years.He also worked for Burroughs in Scotland, Nortel/BNR in Canada, and Cadence Design Systems, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimisation) from the University of Waterloo, Canada, in 1977 and 1978. As a consultant, Grant worked with d-Matrix and other large and small companies in the areas of DSP and configurable processor architecture and design. This work has included market and technical analysis of RISC-V based processors and other configurable processors; detailed design of vector processors for embedded AI applications; and ISA architecting of new DSPs. Grant is a co-author or co-editor of ten books dealing with SoC design, SystemC, UML, modelling, EDA for integrated circuits and system-level design, including the first book on SoC design published in Russian. He was co-chair of the DAC Technical Programme Committee for Methods for 2005 and 2006. His particular areas of interest include DSPs and configurable processors, functional safety solutions including Software Test Libraries and for AI/ML on neural net accelerators, RISC-V instruction set architectures and applications, system-level design, IP-based design of system-on-chip, platform-based design, application-specific instruction set processors, and embedded software. He is a co-editor of the Springer series on embedded systems. Grant is a Senior Member of the IEEE. Specialties: configurable processors, Tensilica, Xtensa, TiE, RISC-V, Electronic Design Automation, System-on-Chip Design methodology, System-Level Design, Platform Based Design, ESL, EDA, SoC, functional safety and cybersecurity of embedded systems (automotive), including functional safety architectures for AI/ML, automated DSP development methodology, Software Test Libraries (STLs) for configurable processors and DSPs

Grant Martin currently works in the None |

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Grant Martin has prior
experience in the following industries:
Self Employed | Cadence Design Systems | Tensilica | Northern Telecom | Bell Northern Research | Burroughs Machines

Grant Martin has the following professional experience:
None | Self Employed | Cadence Design Systems | Tensilica | Northern Telecom | Bell Northern Research | Burroughs Machines