Eduardo Boemo Email & Phone Number | Titular Professor on Logic Design and ASIC Design at the School of Engineering (EPS), Universidad Autónoma de Madrid, Spain (UAM). Honorary professor at CAECE University, Argentine. Ph.D. in Telecom Engineering from the Universidad Politécnica de Madrid, Spain, and Electrical Engineer degree from the Universidad Nacional de Mar del Plata, Argentine. Associated Professor at the ETSI Telecomunicación (UPM) from 1989 to 1996. General Chairman of FPL 2006, SPL (2008, 2007, and 2006 editions), JCRA (2007 and 2003 editions). Director of the EUROFORM Spanish Pole, an organization to provide professional training on FPGAs. Member of Technical Committees of FPGA conferences. Associate Editor of the ACM Transactions on Reconfigurable Systems. Member of the Editorial Board of the Journal of Low-Power Electronics. Co-editor of the Special Issue on FPGAs of the IET Computer & Digital Techniques Journal (July, 2007). Projects, Papers, Ph.D.Thesis, Seminars and Courses are focused on FPGA-related Methodologies. In particular: Area–Time-Power-Thermal Optimization, Synchronization, and E.E. Education.

Eduardo Boemo

Titular Professor on Logic Design and ASIC Design at the School of Engineering (EPS), Universidad Au...
Greater Madrid Metropolitan Area, Greater Madrid Metropolitan Area, Spain

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Eduardo Boemo’s Email eduardo.boemo@uam.es

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Eduardo Boemo’s Location Greater Madrid Metropolitan Area, Greater Madrid Metropolitan Area, Spain

Eduardo Boemo’s Current Industry Escuela Politecnica Superior Universidad Autonoma De Madrid

Eduardo Boemo’s Prior Industry Etsi Telecomunicacion Universidad Politecnica De Madrid

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Work Experience

Escuela Politecnica Superior Universidad Autonoma De Madrid

Profesor Titular

1996-09-01 00:00:00 - Present

Etsi Telecomunicacion Universidad Politecnica De Madrid

Profesor Asociado

1989-01-01 00:00:00 - 1996-01-01 00:00:00

Skills

No Skills Available

Languages

No Languages Available

FAQ About Eduardo Boemo

Eduardo Boemo is located at
Greater Madrid Metropolitan Area, Greater Madrid Metropolitan Area, Spain

Eduardo Boemo is a Titular Professor on Logic Design and ASIC Design at the School of Engineering (EPS), Universidad Autónoma de Madrid, Spain (UAM). Honorary professor at CAECE University, Argentine. Ph.D. in Telecom Engineering from the Universidad Politécnica de Madrid, Spain, and Electrical Engineer degree from the Universidad Nacional de Mar del Plata, Argentine. Associated Professor at the ETSI Telecomunicación (UPM) from 1989 to 1996. General Chairman of FPL 2006, SPL (2008, 2007, and 2006 editions), JCRA (2007 and 2003 editions). Director of the EUROFORM Spanish Pole, an organization to provide professional training on FPGAs. Member of Technical Committees of FPGA conferences. Associate Editor of the ACM Transactions on Reconfigurable Systems. Member of the Editorial Board of the Journal of Low-Power Electronics. Co-editor of the Special Issue on FPGAs of the IET Computer & Digital Techniques Journal (July, 2007). Projects, Papers, Ph.D.Thesis, Seminars and Courses are focused on FPGA-related Methodologies. In particular: Area–Time-Power-Thermal Optimization, Synchronization, and E.E. Education.

Eduardo Boemo currently works in the Escuela Politecnica Superior Universidad Autonoma De Madrid |

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Eduardo Boemo has prior
experience in the following industries:
Etsi Telecomunicacion Universidad Politecnica De Madrid

Eduardo Boemo has the following professional experience:
Escuela Politecnica Superior Universidad Autonoma De Madrid | Etsi Telecomunicacion Universidad Politecnica De Madrid