Dionisio Minopoli Email & Phone Number | More than 21 years experience in Semiconductor Industry, with focus on Memory storage devices. Experience ranges from memory components design (NOR, NAND and PCM flashes) to innovative system architecture definition (UFS, NVMe) based on Emerging Technologies (3DXP), and validation through system modeling (SystemC, TLM, Python, Gem5). FW architecture for mNAND UFS devices for Automotive and Mobile customers. Focus on main data paths and media management algorithms definition and optimization. Nand flash memories OneNAND architectures, digital circuit blocks design and implementation (MICRO, FSM, Address Counters, ECC Circuits, Internal & External Datapath, P/E/R Algorithm implementation), VHDL fullchip verification, VHDL simulation environment setup, microprobing debug on die and wafer. MLC Nand flash memories architecture, digital circuit blocks design and implementation (Address Counters, Datapath), Full Digital Design Flow Development: Floorplan definition, Logical and Physical Synthesys, Clook Tree, P&R, STA. Company tutor in "Neapolis Innovation Campus" [HSIM-NCSIM Transistor level-RTL Cosimulation Flow Development]

Dionisio Minopoli

More than 21 years experience in Semiconductor Industry, with focus on Memory storage devices. Exp...
Naples, Campania, Italy

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Dionisio Minopoli’s Location Naples, Campania, Italy

Dionisio Minopoli’s Current Industry Micron Technology

Dionisio Minopoli’s Prior Industry Numonyx | St Microelectronics

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Senior Member Of Technical Staff - mNAND FW Architect

2020-11-01 00:00:00 - Present

IC Senior Design Engineer

2008-04-01 00:00:00 - 2010-05-01 00:00:00

IC Senior Design Engineer

2001-10-01 00:00:00 - 2008-03-01 00:00:00

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Dionisio Minopoli is a More than 21 years experience in Semiconductor Industry, with focus on Memory storage devices. Experience ranges from memory components design (NOR, NAND and PCM flashes) to innovative system architecture definition (UFS, NVMe) based on Emerging Technologies (3DXP), and validation through system modeling (SystemC, TLM, Python, Gem5). FW architecture for mNAND UFS devices for Automotive and Mobile customers. Focus on main data paths and media management algorithms definition and optimization. Nand flash memories OneNAND architectures, digital circuit blocks design and implementation (MICRO, FSM, Address Counters, ECC Circuits, Internal & External Datapath, P/E/R Algorithm implementation), VHDL fullchip verification, VHDL simulation environment setup, microprobing debug on die and wafer. MLC Nand flash memories architecture, digital circuit blocks design and implementation (Address Counters, Datapath), Full Digital Design Flow Development: Floorplan definition, Logical and Physical Synthesys, Clook Tree, P&R, STA. Company tutor in "Neapolis Innovation Campus" [HSIM-NCSIM Transistor level-RTL Cosimulation Flow Development]