David Kubalek Email & Phone Number | IC design and IC pre-silicon verification Design of Analog/Mixed Signal integrated circuits mainly in Cadence Virtuoso ADE L/XL (Analog) and Cadence Virtuoso AMSdesigner (Mixed Signal) environment, with respect to automotive reliability and safety requirements, including various kinds of simulations, e.g. ESD, EMC, post-layout or electrothermal simulations IC layout/physical design Full custom Analog/Mixed Signal layout, Layout verification (Diva, Calibre), Floorplaning, Chiplevel layout, VCAR automatic router, Parasitic extraction (including 3D field solver), Tapeout arrangement, FIB coordination IC post-silicon evaluation Usage of lab equipment, Handling of the wafer probing station, Definition of test programs for ATE IC technology Model-Hardware Correlation, Design of test structures

David Kubalek

IC design and IC pre-silicon verification Design of Analog/Mixed Signal integrated circuits mainly i...
Czechia, Czechia, Czech Republic

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David Kubalek’s Location Czechia, Czechia, Czech Republic

David Kubalek’s Current Industry Bosch Sensortec

David Kubalek’s Prior Industry Globalfoundries | Infineon Technologies | Stmicroelectronics

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Asic Development Expert

2021-07-01 00:00:00 - Present

Principal Engineer

2015-08-01 00:00:00 - 2015-12-01 00:00:00

Analog/Mixed Signal Ic Senior Engineer

2013-01-01 00:00:00 - 2015-07-01 00:00:00

Analog Ic Layout Engineer

2003-09-01 00:00:00 - 2007-04-01 00:00:00

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David Kubalek is a IC design and IC pre-silicon verification Design of Analog/Mixed Signal integrated circuits mainly in Cadence Virtuoso ADE L/XL (Analog) and Cadence Virtuoso AMSdesigner (Mixed Signal) environment, with respect to automotive reliability and safety requirements, including various kinds of simulations, e.g. ESD, EMC, post-layout or electrothermal simulations IC layout/physical design Full custom Analog/Mixed Signal layout, Layout verification (Diva, Calibre), Floorplaning, Chiplevel layout, VCAR automatic router, Parasitic extraction (including 3D field solver), Tapeout arrangement, FIB coordination IC post-silicon evaluation Usage of lab equipment, Handling of the wafer probing station, Definition of test programs for ATE IC technology Model-Hardware Correlation, Design of test structures