David Faubert Email & Phone Number | ASIC Verification Design Engineer for DDR high-speed memory physical interface, PHY, test chips. Synopsys ARC-processor embedded system DDR PHYs and associated customer-delivery software.

David Faubert

ASIC Verification Design Engineer for DDR high-speed memory physical interface, PHY, test chips. Sy...
Synopsys, 1 Antares Dr Suite 300, Canada

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David Faubert’s Location Synopsys, 1 Antares Dr Suite 300, Canada

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Senior R&D Engineer

2007-07-01 00:00:00 - 2023-11-01 00:00:00

ASIC Design Engineer

2006-02-01 00:00:00 - 2007-07-01 00:00:00

Unemployed Parent of Toddlers

2001-12-01 00:00:00 - 2006-02-01 00:00:00

Senior ASIC Designer

2001-05-01 00:00:00 - 2001-12-01 00:00:00

ASIC Designer

1999-08-01 00:00:00 - 2001-05-01 00:00:00

Avionics Designer

1995-07-01 00:00:00 - 1997-10-01 00:00:00

Systems Engineer

1992-07-01 00:00:00 - 1995-05-01 00:00:00

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David Faubert is a ASIC Verification Design Engineer for DDR high-speed memory physical interface, PHY, test chips. Synopsys ARC-processor embedded system DDR PHYs and associated customer-delivery software.

David Faubert has prior
experience in the following industries:
Synopsys | Mosaid | My Family | Zucotto Wireless | Nortel Networks | Canadian Marconi | Macdonald Dettwiler And Associates

David Faubert has the following professional experience:
Synopsys | Mosaid | My Family | Zucotto Wireless | Nortel Networks | Canadian Marconi | Macdonald Dettwiler And Associates