Dat Nguyen Email & Phone Number | Over 14+ years of industry experience in ASIC physical design implementation, design methodology development and design process management. A problem solver to all backend issues in Physical Verification, Antenna, Layout Vs Schematic, ESD, RH static and dynamic EMIR, Xtalk, and Signal Integrity. Not just a tool user, - a real tool expert, problem solver, developer and user, with a proven track record over many high profile projects. Successfully lead physical design activities over 50 ASIC programs from netlist to gdsii, ranging in gate counts up to 110 million logic gates, Frequencies up to 1Ghz and Technologies from 440nm to 40nm. Completed the designs with many different tools, Magma, Synopsys, Cadence EDI, AVANT!, AQUARIUSXO. Over 14 years of working with cross-functional teams. Excels at working within a team in a technical and mentoring role. Strengths include multi-tasking and problem solving. Long track record of driving latest technology node, largest capacity and highest performance designs. Physical Design Experience includes IO Ring Implementation, Power Grid Implementation, Hierarchical Design Planning, Block Level design, and all final signoff checks, DRC, ANTENNA, LVS, ESD, RH Static and Dynamic EMIR, Xtalk, Signal Integrity, and FIB setup for Silicon debug. Defined and developed the power routing methodology for TI ASIC organization. Recognized power route expert and responsible for methodology review on all 40nm designs.

Dat Nguyen

Over 14+ years of industry experience in ASIC physical design implementation, design methodology dev...
Garland, Texas, United States

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Dat Nguyen’s Email dat@ti.com

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Dat Nguyen’s Location Garland, Texas, United States

Dat Nguyen’s Current Industry Texas Instruments Texas Instruments Embedded Processing

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ASIC Physical Design Engineer

1998-08-01 00:00:00 - Present

Physical Design Engineer - Member Group Technical Staff (Emeritus)

1998-08-01 00:00:00 - Present

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Dat Nguyen is a Over 14+ years of industry experience in ASIC physical design implementation, design methodology development and design process management. A problem solver to all backend issues in Physical Verification, Antenna, Layout Vs Schematic, ESD, RH static and dynamic EMIR, Xtalk, and Signal Integrity. Not just a tool user, - a real tool expert, problem solver, developer and user, with a proven track record over many high profile projects. Successfully lead physical design activities over 50 ASIC programs from netlist to gdsii, ranging in gate counts up to 110 million logic gates, Frequencies up to 1Ghz and Technologies from 440nm to 40nm. Completed the designs with many different tools, Magma, Synopsys, Cadence EDI, AVANT!, AQUARIUSXO. Over 14 years of working with cross-functional teams. Excels at working within a team in a technical and mentoring role. Strengths include multi-tasking and problem solving. Long track record of driving latest technology node, largest capacity and highest performance designs. Physical Design Experience includes IO Ring Implementation, Power Grid Implementation, Hierarchical Design Planning, Block Level design, and all final signoff checks, DRC, ANTENNA, LVS, ESD, RH Static and Dynamic EMIR, Xtalk, Signal Integrity, and FIB setup for Silicon debug. Defined and developed the power routing methodology for TI ASIC organization. Recognized power route expert and responsible for methodology review on all 40nm designs.