Chuan Thim Khor Email & Phone Number | Engineering professional with 17 years of experience in mixed-signal circuit designs on both state-of-the-art Intel and TSMC technologies with proven successes in architectural pathfinding, circuit design as well as functional and performance validations in simulation and silicon environments. Leading a technical team who constantly striving towards the goal for best-in-class IP in terms of Performance, Power and Area (PPA) by innovating microarchitectural enhancements. • Pioneered the first Advanced Interface Bus (AIB) with mushrooming proliferation in Intel PSG’s 2.5D initiatives • Leading design and execution of 2.5D clocking developments • In-depth knowledge on mixed-signal clocking (Transceiver, PLL, CDR, DLL, DCC, CDN, etc.) and analog circuits (regulators, bias generators, etc.) • Experienced in ASIC design flow and methodology covering Verilog coding, STA timing closure and design quality signoff checks • Exposure to various Fault Isolation Failure Analysis (FIFA) techniques (EMMI, IREM, LADA, Nano- & Pico- Probing, etc.) with proven track record on resolution of challenging silicon issues • Skilled users with extensive hands-on experience on EDA tools, flow & methodology: Cadence (Virtuoso and ADEL/XL), Hspice, Hsim, Finesim, MOSRA, StarRC XT, CosmosScope, Waveview, Totem, SpyGlass Lint, VCS, Primetime STA, DC Compiler, IC Compiler II • Proficient in programming and scripting languages: Verilog, Linux/Unix shell, Perl, Python

Chuan Thim Khor

Engineering professional with 17 years of experience in mixed-signal circuit designs on both state-o...
Malaysia

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Chuan Thim Khor’s Email ckhor@altera.com

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Chuan Thim Khor’s Location Malaysia

Chuan Thim Khor’s Current Industry Intel

Chuan Thim Khor’s Prior Industry Altera

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System-on-Chip Design Engineer

2016-04-01 00:00:00 - Present

Senior Member of Technical Staff

2006-06-01 00:00:00 - 2016-04-01 00:00:00

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Chuan Thim Khor is a Engineering professional with 17 years of experience in mixed-signal circuit designs on both state-of-the-art Intel and TSMC technologies with proven successes in architectural pathfinding, circuit design as well as functional and performance validations in simulation and silicon environments. Leading a technical team who constantly striving towards the goal for best-in-class IP in terms of Performance, Power and Area (PPA) by innovating microarchitectural enhancements. • Pioneered the first Advanced Interface Bus (AIB) with mushrooming proliferation in Intel PSG’s 2.5D initiatives • Leading design and execution of 2.5D clocking developments • In-depth knowledge on mixed-signal clocking (Transceiver, PLL, CDR, DLL, DCC, CDN, etc.) and analog circuits (regulators, bias generators, etc.) • Experienced in ASIC design flow and methodology covering Verilog coding, STA timing closure and design quality signoff checks • Exposure to various Fault Isolation Failure Analysis (FIFA) techniques (EMMI, IREM, LADA, Nano- & Pico- Probing, etc.) with proven track record on resolution of challenging silicon issues • Skilled users with extensive hands-on experience on EDA tools, flow & methodology: Cadence (Virtuoso and ADEL/XL), Hspice, Hsim, Finesim, MOSRA, StarRC XT, CosmosScope, Waveview, Totem, SpyGlass Lint, VCS, Primetime STA, DC Compiler, IC Compiler II • Proficient in programming and scripting languages: Verilog, Linux/Unix shell, Perl, Python